Open AurelienUoU opened 4 years ago
synth -run coarse
only runs the "coarse" label of synth
, which does not include hierarchy and therefore modules aren't elaborated before proc with the proper parameters. Run hierarchy -top ...
before synth -run coarse
, or use synth -run :fine -top
to run both hierarchy and coarse synthesis (:fine
means everything up to but not including the fine
label)
Thanks for your quick answer!
I updated the script (and the repo) according to your advice. It appears than my top module "LMAC_CORE_TOP_SYNCH" is pushed down to "LMAC_CORE_TOP". It's not really a big deal and I figured it out relatively quickly. However, it can be painful to often checking this.
I updated the script (and the repo) according to your advice. It appears than my top module "LMAC_CORE_TOP_SYNCH" is pushed down to "LMAC_CORE_TOP".
Can you elaborate what you mean here?
My top module is LMAC_CORE_TOP_SYNTH, it's just a wrapper of LMAC_CORE_TOP who's merging rclk and wclk into clk. However, after all the netlists are read the module LMAC_CORE_TOP_SYNTH is no longer available. For example, "hierarchy -top LMAC_CORE_TOP_SYNTH" fails because this module "doesn't exist". If I use "hierarchy -top LMAC_CORE_TOP" everything works well. The clock merging is propagated into LMAC_CORE_TOP. If I do not read LMAC_CORE_TOP_SYNTH.v and still use "hierarchy -top LMAC_CORE_TOP" my fifo is not correctly map to the mono-clock DPRAM.
BTW, about the synth
command. Documentation shows hierarchy
is done as "begin" and as far as I understood synth -run coarse
should run "begin" and "coarse" parts. Or, should I do synth -run begin
then synth -run coarse
?
synth -run coarse
runs just the coarse label part. To run both hierarchy and coarse, use synth -run :fine
(everything up to but not including the fine label)
Looking again at the top module bug,
However, after all the netlists are read the module LMAC_CORE_TOP_SYNTH is no longer available. For example, "hierarchy -top LMAC_CORE_TOP_SYNTH" fails because this module "doesn't exist".
Seems like it is not parsing LMAC_CORE_TOP_SYNTH correctly, but something odd is going on as neither Verilator nor iverilog do either
God knows where that file came from, but seems like the problem is some of the spaces are actually UTF-8 U+2008 "punctuation spaces" rather than normal ASCII ones.
iconv -f utf-8 -t ascii//TRANSLIT Verilog_netlists/full_design/LMAC_CORE_TOP_SYNTH.v > Verilog_netlists/full_design/LMAC_CORE_TOP_SYNTH_ascii.v && mv Verilog_netlists/full_design/LMAC_CORE_TOP_SYNTH_ascii.v Verilog_netlists/full_design/LMAC_CORE_TOP_SYNTH.v
is a workaround for this, but perhaps Yosys should be failing more gracefully in this case.
Just FYI, the code comes from one of the modules at https://github.com/lewiz-support
I don't think the problematic file (LMAC_CORE_TOP_SYNTH) does - I'm mostly curious what kind of editor is actually inserting these characters...
Dear community,
I encountered issues to flatten a design while I try to synthesize and techmap it with the latest version of Yosys. Design is dual-clock with a wrapper on top to merge read and write clocks. A small case works but the full design doesn't.
The issue appears at the first "synth" step using the flag "-flatten".
All the elements (scripts, netlits etc...) can be found at https://github.com/AurelienUoU/fifo_to_one_clock_dpram.git
Sincerely, Aurelien