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Yosys Open SYnthesis Suite
https://yosyshq.net/yosys/
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Xilinx's RAMB36 inference #1748

Open tmichalak opened 4 years ago

tmichalak commented 4 years ago

Steps to reproduce the issue

minitest_bram_36.zip

Run make bram.edif to call yosys Run make bram_vivado.bit to call vivado

Expected behavior

Yosys should infere a RAMB36 TDP as Vivado does.

Actual behavior

Yosys fails to infer the BRAM

2.52. Printing statistics.

=== bram ===

   Number of wires:                 26
   Number of wire bits:            364
   Number of public wires:          12
   Number of public wire bits:     150  
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                153
     $mem                            1
     IBUF                           86
     LUT2                            2
     OBUF                           64

   Estimated number of LCs:          1
mwkmwkmwk commented 4 years ago

Known issue, yosys only supports SDP memories. Fixing this will likely require a full redesign of the memory_bram pass and won't happen any time soon (see the discussion at #1134)