Closed rodrigomelo9 closed 3 years ago
This example requires support for FFs with both asynchronous set and reset, which we currently don't have in the xilinx flow. Adding support for older families (xc5v and before) would be pretty trivial, but for xc7 we need to emulate those with some tricky circuits, as such things are not directly supported in hardware anymore.
This issue should be fixed as of several months ago when the dfflegalize
patchset landed — can you recheck with current yosys?
Great @mwkmwkmwk I will check and let you know!
It works! :clap::clap::clap: It can be closed. Thanks!
I was comparing Yosys against ISE and Vivado, using examples provided by Xilinx. I want to remarks that from 178 examples, only 12 failed using Yosys + ISE as backend, and 11 are related with memory inferences (maybe all of them are true dual-port, I will check and comment in #1802 ). Here a counter example which failed.
It was synthesized (without problems) using Yosys:
The ISE error is:
Using pure ISE (xst as synthesizer) the implementation finish without problems.