ERROR: Abort in frontends/ast/simplify.cc:4239.

[paul-cerb]

Steps to reproduce the issue

Applies to Yosys 0.9+2406 (git sha1 a9b61080, clang 10.0.0-4ubuntu1 -fPIC -Os) Crashing on read_verilog

I have narrowed down the crash to the following code fragment:

 // Signals
 reg [2:0] xbar_0_arb_0_select;
 reg [3:0] xbar_0_arb_0_sel_0_c [0:3-1];
 reg [2:0] xbar_0_arb_0_access;

 // Select based on weight
 always @(xbar_0_arb_0_access, xbar_0_arb_0_sel_0_c[0], xbar_0_arb_0_sel_0_c[1], xbar_0_arb_0_sel_0_c[2]) begin: HSM_TOP_XBAR_0_ARB_0_SEL_0__SEL
     integer t;
     integer m;
     integer i;
     xbar_0_arb_0_select = 0;
     t = 0;
     m = 0;
     for (i=0; i<3; i=i+1) begin
         if (xbar_0_arb_0_access[i]) begin
             if ((xbar_0_arb_0_sel_0_c[i] >= m)) begin
                 m = xbar_0_arb_0_sel_0_c[i];
                 t = i;
             end
         end
     end
     if (m) begin
         xbar_0_arb_0_select[t] = 1'b1; // *BUG*
     end
 end

Work Around:

Replacing the bugged line with the following alternative is work around for the issue xbar_0_arb_0_select = 1<<t ; // NO BUG

Expected behavior

No crash on read_verilog

Actual behavior

ERROR: Abort in frontends/ast/simplify.cc:4239. Command exited with non-zero status 1

[daveshah1]

See #2241 which also has an alternative workaround.

[paul-cerb]

Thank you very much for that amazingly fast reply! I'm afraid I didn't find #2241, sorry to take up your time. I'm relatively new to Yosys and will need to find my way around a bit better.

I haven't tried the 'always @', which I know is better practice, as the code is auto-generated using MyHDL, but it's helpful to know. I'll check to see if the back end code generator has that option and if not I think it should* be relatively easy to update.

[clairexen]

Unfortunately the OP does not contain a MCVE (the C part of that acronym isn't satisfied). I think #2256 that just closed #2241 also fixed this one.