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Yosys Open SYnthesis Suite
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DFFLIBMAP error #2504

Closed 1347806 closed 3 years ago

1347806 commented 3 years ago

Steps to reproduce the issue

i am a freashman about yosys. I wonder if yosys can support other lib like TSMC 65nm lib? I want try use yosys to synthesize the foo.v with tcbn65lpbwp12tlvttc.lib which is provided by TSMC. Below is tcl

!/usr/bin/env yosys

read_verilog -sv foo.v hierarchy -top foo proc; opt; techmap; opt dfflibmap -liberty /home/yanan/ic_design/tt/tcbn65lpbwp12tlvttc.lib abc -liberty /home/yanan/ic_design/tt/tcbn65lpbwp12tlvttc.lib

module foo ( input a, input b, input c, output o );

assign o = (a & b) | c;

endmodule

and there is log

/----------------------------------------------------------------------------\ yosys -- Yosys Open SYnthesis Suite
Copyright (C) 2012 - 2016 Clifford Wolf clifford@clifford.at
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

----------------------------------------------------------------------------/

Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os)

-- Executing script file `foo.ys' --

  1. Executing Verilog-2005 frontend. Parsing SystemVerilog input from foo.v' to AST representation. Generating RTLIL representation for module\foo'. Successfully finished Verilog frontend.

  2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy.. Top module: \foo

2.2. Analyzing design hierarchy.. Top module: \foo Removed 0 unused modules.

  1. Executing PROC pass (convert processes to netlists).

3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches.

3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases.

3.3. Executing PROC_INIT pass (extract init attributes).

3.4. Executing PROC_ARST pass (detect async resets in processes).

3.5. Executing PROC_MUX pass (convert decision trees to multiplexers).

3.6. Executing PROC_DLATCH pass (convert process syncs to latches).

3.7. Executing PROC_DFF pass (convert process syncs to FFs).

3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches.

  1. Executing OPT pass (performing simple optimizations).

4.1. Executing OPT_EXPR pass (perform const folding).

4.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\foo'. Removed a total of 0 cells.

4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \foo.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports.

4.4. Executing OPTREDUCE pass (consolidate $*mux and $reduce* inputs). Optimizing cells in module \foo. Performed a total of 0 changes.

4.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\foo'. Removed a total of 0 cells.

4.6. Executing OPT_RMDFF pass (remove dff with constant values).

4.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \foo..

4.8. Executing OPT_EXPR pass (perform const folding).

4.9. Finished OPT passes. (There is nothing left to do.)

  1. Executing TECHMAP pass (map to technology primitives).

5.1. Executing Verilog-2005 frontend. Parsing Verilog input from <techmap.v>' to AST representation. Generating RTLIL representation for module_90_simplemap_bool_ops'. Generating RTLIL representation for module \_90_simplemap_reduce_ops'. Generating RTLIL representation for module_90_simplemap_logic_ops'. Generating RTLIL representation for module \_90_simplemap_compare_ops'. Generating RTLIL representation for module_90_simplemap_various'. Generating RTLIL representation for module \_90_simplemap_registers'. Generating RTLIL representation for module_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module \_90_shift_shiftx'. Generating RTLIL representation for module_90_fa'. Generating RTLIL representation for module \_90_lcu'. Generating RTLIL representation for module_90_alu'. Generating RTLIL representation for module \_90_macc'. Generating RTLIL representation for module_90_alumacc'. Generating RTLIL representation for module \$__div_mod_u'. Generating RTLIL representation for module\$__div_mod'. Generating RTLIL representation for module \_90_div'. Generating RTLIL representation for module_90_mod'. Generating RTLIL representation for module \_90_pow'. Generating RTLIL representation for module_90_pmux'. Generating RTLIL representation for module `_90_lut'. Successfully finished Verilog frontend. Mapping foo.$and$foo.v:8$1 ($and) with simplemap. Mapping foo.$or$foo.v:8$2 ($or) with simplemap. No more expansions possible.

  1. Executing OPT pass (performing simple optimizations).

6.1. Executing OPT_EXPR pass (perform const folding).

6.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\foo'. Removed a total of 0 cells.

6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \foo.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports.

6.4. Executing OPTREDUCE pass (consolidate $*mux and $reduce* inputs). Optimizing cells in module \foo. Performed a total of 0 changes.

6.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\foo'. Removed a total of 0 cells.

6.6. Executing OPT_RMDFF pass (remove dff with constant values).

6.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \foo..

6.8. Executing OPT_EXPR pass (perform const folding).

6.9. Finished OPT passes. (There is nothing left to do.)

  1. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). ERROR: Syntax error in line 73.

the tcl can run correctly with qflow lib osu018.lib but occur error with tmsc lib,So i wonder if the yosys can support other lib? PS: Syntax error in line 73 come from which tcl? how to debug it？

Ravenslofty commented 3 years ago

The syntax error comes from line 73 of the Liberty file, not from your TCL script. You'd have to paste that somewhere for me to tell what's going on.

Note also that dfflibmap is a bit limited in what it can and can't infer (e.g. DFFs with enable are not recognised).

1347806 commented 3 years ago

The syntax error comes from line 73 of the Liberty file, not from your TCL script. You'd have to paste that somewhere for me to tell what's going on.

Note also that dfflibmap is a bit limited in what it can and can't infer (e.g. DFFs with enable are not recognised). thank you for your reply below are line 72-77 from tmsc lib input_voltage(cmos) { vil : 0.3 VDD ; vih : 0.7 VDD ; vimin : -0.5 ; vimax : VDD + 0.5 ; }

the lib has power information. I del all the power information but ERROR: Syntax error in line 469 below are line 459-471 and the bold line is line 469.So I think the error may come from other scipt and I find the dfflibmap.cc file I can only understand some simple syntax but from what I got , I think the yosys can not supprot other lib. Am I right?

 fall_transition (delay_template_7x7_0) {
    index_1 ("0.0042, 0.0099, 0.0212, 0.0439, 0.0893, 0.1801, 0.3618");
    index_2 ("0.00072, 0.00146, 0.00294, 0.0059, 0.01183, 0.02367, 0.04736");
    values ( \
      "0.01733, 0.02299, 0.03444, 0.0579, 0.1055, 0.2005, 0.3907", \
      "0.01734, 0.02298, 0.03447, 0.05786, 0.1054, 0.2007, 0.3909", \
      "0.01733, 0.023, 0.03444, 0.0579, 0.1055, 0.2004, 0.3907", \
      "0.01741, 0.02302, 0.0345, 0.05791, 0.1053, 0.2007, 0.3909", \
       "0.01838, 0.02381, 0.03494, 0.05803, 0.1056, 0.2007, 0.3912", \                                                 line 469
      "0.02074, 0.0257, 0.03623, 0.05874, 0.1055, 0.2007, 0.3907", \
      "0.0249, 0.02968, 0.03934, 0.06039, 0.1061, 0.2008, 0.391" \
    );
  }
Ravenslofty commented 3 years ago

Yes, for example, the SkyWater open PDK is supported.

On Mon, 28 Dec 2020, 07:51 1347806, notifications@github.com wrote:

The syntax error comes from line 73 of the Liberty file, not from your TCL script. You'd have to paste that somewhere for me to tell what's going on.

Note also that dfflibmap is a bit limited in what it can and can't infer (e.g. DFFs with enable are not recognised).

I find the dfflibmap.cc file which is used to map the cell to lib but thank you for your reply anyway. Do you know if the yosys can support other lib?

— You are receiving this because you commented. Reply to this email directly, view it on GitHub https://github.com/YosysHQ/yosys/issues/2504#issuecomment-751620046, or unsubscribe https://github.com/notifications/unsubscribe-auth/AALPDW7MFBXPQWZOFX66P73SXA2IDANCNFSM4VJ4GTTQ .

1347806 commented 3 years ago

Yes, for example, the SkyWater open PDK is supported. … On Mon, 28 Dec 2020, 07:51 1347806, @.***> wrote: The syntax error comes from line 73 of the Liberty file, not from your TCL script. You'd have to paste that somewhere for me to tell what's going on. Note also that dfflibmap is a bit limited in what it can and can't infer (e.g. DFFs with enable are not recognised). I find the dfflibmap.cc file which is used to map the cell to lib but thank you for your reply anyway. Do you know if the yosys can support other lib? — You are receiving this because you commented. Reply to this email directly, view it on GitHub <#2504 (comment)>, or unsubscribe https://github.com/notifications/unsubscribe-auth/AALPDW7MFBXPQWZOFX66P73SXA2IDANCNFSM4VJ4GTTQ .

Yes, for example, the SkyWater open PDK is supported. … On Mon, 28 Dec 2020, 07:51 1347806, @.***> wrote: The syntax error comes from line 73 of the Liberty file, not from your TCL script. You'd have to paste that somewhere for me to tell what's going on. Note also that dfflibmap is a bit limited in what it can and can't infer (e.g. DFFs with enable are not recognised). I find the dfflibmap.cc file which is used to map the cell to lib but thank you for your reply anyway. Do you know if the yosys can support other lib? — You are receiving this because you commented. Reply to this email directly, view it on GitHub <#2504 (comment)>, or unsubscribe https://github.com/notifications/unsubscribe-auth/AALPDW7MFBXPQWZOFX66P73SXA2IDANCNFSM4VJ4GTTQ .

Yes, for example, the SkyWater open PDK is supported. … On Mon, 28 Dec 2020, 07:51 1347806, @.***> wrote: The syntax error comes from line 73 of the Liberty file, not from your TCL script. You'd have to paste that somewhere for me to tell what's going on. Note also that dfflibmap is a bit limited in what it can and can't infer (e.g. DFFs with enable are not recognised). I find the dfflibmap.cc file which is used to map the cell to lib but thank you for your reply anyway. Do you know if the yosys can support other lib? — You are receiving this because you commented. Reply to this email directly, view it on GitHub <#2504 (comment)>, or unsubscribe https://github.com/notifications/unsubscribe-auth/AALPDW7MFBXPQWZOFX66P73SXA2IDANCNFSM4VJ4GTTQ .

thank you for your help. I search the SkyWater open PDK and find it in github. But it just support 130nm process. Do you know about any other open soucer tool can support process like 65nm and even more adcanced process like 40nm and 28nm?

Ravenslofty commented 3 years ago

Again, the problem is line 73 of the TSMC Liberty file you're passing to Yosys, and unless you upload that line, we can't fix it so that Yosys does support that library. It's nothing to do with the feature size of the target, simply a syntax that we don't presently accept.

And no, to my knowledge nothing else open-source comes close to Yosys's support of PDKs.

On Mon, 28 Dec 2020, 12:58 1347806, notifications@github.com wrote:

Yes, for example, the SkyWater open PDK is supported. … <#m9198856471364192800> On Mon, 28 Dec 2020, 07:51 1347806, @.***> wrote: The syntax error comes from line 73 of the Liberty file, not from your TCL script. You'd have to paste that somewhere for me to tell what's going on. Note also that dfflibmap is a bit limited in what it can and can't infer (e.g. DFFs with enable are not recognised). I find the dfflibmap.cc file which is used to map the cell to lib but thank you for your reply anyway. Do you know if the yosys can support other lib? — You are receiving this because you commented. Reply to this email directly, view it on GitHub <#2504 (comment) https://github.com/YosysHQ/yosys/issues/2504#issuecomment-751620046>, or unsubscribe https://github.com/notifications/unsubscribe-auth/AALPDW7MFBXPQWZOFX66P73SXA2IDANCNFSM4VJ4GTTQ .

Yes, for example, the SkyWater open PDK is supported. … <#m9198856471364192800> On Mon, 28 Dec 2020, 07:51 1347806, @.***> wrote: The syntax error comes from line 73 of the Liberty file, not from your TCL script. You'd have to paste that somewhere for me to tell what's going on. Note also that dfflibmap is a bit limited in what it can and can't infer (e.g. DFFs with enable are not recognised). I find the dfflibmap.cc file which is used to map the cell to lib but thank you for your reply anyway. Do you know if the yosys can support other lib? — You are receiving this because you commented. Reply to this email directly, view it on GitHub <#2504 (comment) https://github.com/YosysHQ/yosys/issues/2504#issuecomment-751620046>, or unsubscribe https://github.com/notifications/unsubscribe-auth/AALPDW7MFBXPQWZOFX66P73SXA2IDANCNFSM4VJ4GTTQ .

Yes, for example, the SkyWater open PDK is supported. … <#m9198856471364192800> On Mon, 28 Dec 2020, 07:51 1347806, @.***> wrote: The syntax error comes from line 73 of the Liberty file, not from your TCL script. You'd have to paste that somewhere for me to tell what's going on. Note also that dfflibmap is a bit limited in what it can and can't infer (e.g. DFFs with enable are not recognised). I find the dfflibmap.cc file which is used to map the cell to lib but thank you for your reply anyway. Do you know if the yosys can support other lib? — You are receiving this because you commented. Reply to this email directly, view it on GitHub <#2504 (comment) https://github.com/YosysHQ/yosys/issues/2504#issuecomment-751620046>, or unsubscribe https://github.com/notifications/unsubscribe-auth/AALPDW7MFBXPQWZOFX66P73SXA2IDANCNFSM4VJ4GTTQ .

thank you for your help. I search the SkyWater open PDK and find it in github. But it just support 130nm process. Do you know about any other open soucer tool can support process like 65nm and even more adcanced process like 40nm and 28nm?

— You are receiving this because you commented. Reply to this email directly, view it on GitHub https://github.com/YosysHQ/yosys/issues/2504#issuecomment-751704052, or unsubscribe https://github.com/notifications/unsubscribe-auth/AALPDWZLJ4VDNDYRDCIC3DLSXB6H7ANCNFSM4VJ4GTTQ .

1347806 commented 3 years ago

Again, the problem is line 73 of the TSMC Liberty file you're passing to Yosys, and unless you upload that line, we can't fix it so that Yosys does support that library. It's nothing to do with the feature size of the target, simply a syntax that we don't presently accept. And no, to my knowledge nothing else open-source comes close to Yosys's support of PDKs. … On Mon, 28 Dec 2020, 12:58 1347806, @.> wrote: Yes, for example, the SkyWater open PDK is supported. … <#m9198856471364192800> On Mon, 28 Dec 2020, 07:51 1347806, @.> wrote: The syntax error comes from line 73 of the Liberty file, not from your TCL script. You'd have to paste that somewhere for me to tell what's going on. Note also that dfflibmap is a bit limited in what it can and can't infer (e.g. DFFs with enable are not recognised). I find the dfflibmap.cc file which is used to map the cell to lib but thank you for your reply anyway. Do you know if the yosys can support other lib? — You are receiving this because you commented. Reply to this email directly, view it on GitHub <#2504 (comment) <#2504 (comment)>>, or unsubscribe https://github.com/notifications/unsubscribe-auth/AALPDW7MFBXPQWZOFX66P73SXA2IDANCNFSM4VJ4GTTQ . Yes, for example, the SkyWater open PDK is supported. … <#m9198856471364192800> On Mon, 28 Dec 2020, 07:51 1347806, @.> wrote: The syntax error comes from line 73 of the Liberty file, not from your TCL script. You'd have to paste that somewhere for me to tell what's going on. Note also that dfflibmap is a bit limited in what it can and can't infer (e.g. DFFs with enable are not recognised). I find the dfflibmap.cc file which is used to map the cell to lib but thank you for your reply anyway. Do you know if the yosys can support other lib? — You are receiving this because you commented. Reply to this email directly, view it on GitHub <#2504 (comment) <#2504 (comment)>>, or unsubscribe https://github.com/notifications/unsubscribe-auth/AALPDW7MFBXPQWZOFX66P73SXA2IDANCNFSM4VJ4GTTQ . Yes, for example, the SkyWater open PDK is supported. … <#m9198856471364192800> On Mon, 28 Dec 2020, 07:51 1347806, @.> wrote: The syntax error comes from line 73 of the Liberty file, not from your TCL script. You'd have to paste that somewhere for me to tell what's going on. Note also that dfflibmap is a bit limited in what it can and can't infer (e.g. DFFs with enable are not recognised). I find the dfflibmap.cc file which is used to map the cell to lib but thank you for your reply anyway. Do you know if the yosys can support other lib? — You are receiving this because you commented. Reply to this email directly, view it on GitHub <#2504 (comment) <#2504 (comment)>>, or unsubscribe https://github.com/notifications/unsubscribe-auth/AALPDW7MFBXPQWZOFX66P73SXA2IDANCNFSM4VJ4GTTQ . thank you for your help. I search the SkyWater open PDK and find it in github. But it just support 130nm process. Do you know about any other open soucer tool can support process like 65nm and even more adcanced process like 40nm and 28nm? — You are receiving this because you commented. Reply to this email directly, view it on GitHub <#2504 (comment)>, or unsubscribe https://github.com/notifications/unsubscribe-auth/AALPDWZLJ4VDNDYRDCIC3DLSXB6H7ANCNFSM4VJ4GTTQ .

thank you ！