Closed whitequark closed 7 years ago
Setting a non-existing module parameter creates an error while running the hierarchy
pass. Please post Verilog example code + Yosys script if you have a case where this does not work. (Closing this issue for now.)
I think that doesn't happen when the module is a black box, but I'll let @azonenberg provide the details as I have a flight soon...
Fixed in commit aa72262.
Thank you!
This has caused me problems in the past and now @azonenberg hit it: https://irclog.whitequark.org/.openfpga/2016-10-22#1477116793-1477120132. Do you agree that it is desirable?