Feature request: SystemVerilog static casts

Verilog 2005 specifies that implicit conversion from real to integer should be done by rounding. yosys does this correctly, however it also generates warnings which cannot be removed (without resorting to $rtoi, which does truncation). E.g.

int i;
i = (2.5 * 3.5);

yields

Warning: converting real value 8.750000e+00 to binary 9.

If SystemVerilog static casts were supported, one could be explicit about the cast, and in this case a warning would not be called for:

int i;
i = int'(2.5 * 3.5);

The same code would then also pass through the Verilator linter.

YosysHQ / yosys

Feature request: SystemVerilog static casts #2923