Lattice ECP5: Module `FD1P3DX' does not have a port named 'q'.

[SiliconWizard]

Using Yosys and Yosys GHDL plugin, from this instantiation:

FF_0: FD1P3DX port map (D=>RdAddress(10), SP=>RdClockEn, CK=>RdClock, CD=>'0', Q=>raddr10_ff);

I get the following error at the "3.3.2. Analyzing design hierarchy.." step:

ERROR: Module FD1P3DX' referenced in modulecachedataram' in cell `ff_0' does not have a port named 'q'.

The definition for FD1P3DX seems correct though: https://github.com/YosysHQ/yosys/blob/master/techlibs/ecp5/cells_ff.vh https://github.com/ghdl/ghdl-yosys-plugin/blob/master/library/ecp5u/components.vhdl

[SiliconWizard]

The problem comes from the fact that I was trying to use the original Lattice package for ECP5U components. In it, all component ports contain an initializer: := 'X'; which seems to confuse Yosys. I switched to the 'components.vhdl' from the link I gave above, which is essentially the same definitions but without the port initializers. It fixes the problem.

Example for Lattice definition:

COMPONENT FD1P3DX GENERIC (gsr : String := "ENABLED"); PORT( d : IN std_logic := 'X'; sp: IN std_logic := 'X'; ck: IN std_logic := 'X'; cd: IN std_logic := 'X'; q : OUT std_logic := 'X' ); END COMPONENT;

Same in the GHDL yosys plugin library:

component fd1p3dx is generic ( gsr : string := "ENABLED" ); port ( d : in std_logic; sp : in std_logic; ck : in std_logic; cd : in std_logic; q : out std_logic ); end component;