SiliconWizard
commented
2 years ago This all comes from a case sensitivity issue. This is discussed in here: https://github.com/ghdl/ghdl-yosys-plugin/issues/155
So anyone interested in working with the Lattice ECP5 in VHDL can read this, and more generally using VHDL and blacboxes with Yosys.
Context: using Yosys toolchain on MSYS2, with VHDL source files, using Yosys GHDL plugin. Tried on Linux as well with the latest toolchain built from git, same result.
The exact same primitive instantiation ('ODDRX1F') in the exact same source file, but in two different projects, works in one project, but yields a 'cells_not_processed' attribute in another (again, the source file instantiating it is the same, but there are different source files otherwise).
In Yosys report, this can be seen as 'ODDRX1F' appearing in all uppercase in the cells list when it's correctly processed (first project), and as 'oddrx1f' in all lowercase when it's not processed correctly (second project). I looked at the JSON output, and the difference is this:
First project where it's OK (just pasting the part with a difference):
Second project where it's not:
So as one can see, the only difference seems to be the "cells_not_processed" attribute in the case which fails.
Another difference in the JSON files is that in the second case, there is an additional cell (in all lowercase) like this:
The instantiation is again in the same source file (a SDRAM controller), and it is like so:
Thanks for any pointers. I do not see why this would be treated in a different way in both projects while the instantiation is exactly the same in the same source file.
I encountered a similar issue with another primitive: DP16KD.