Feature request: $random cell for cxxrtl/write_verilog

Background

The Bluespec HDL comes with a number of primitives written in Verilog that are sometimes needed by compiler output. One of these primitives is a module called ConstrainedRandom.v, which uses the simulation-only $random task in order to generate random numbers for use during simulation. This module is one of the only Bluespec "primitive modules" that cannot be handled by Yosys, as it stands today. I would like that to change, so that my tool yosys-bluespec can handle bsc output more reliably, and in turn more easily integrate with Bluespec flows; at the moment I fatally halt compilation if this module is used.

Now, Bluespec itself comes with a robust simulation framework (called "bluesim", a part of the compiler and which leverages the semantics of the language) which can handle this, but an alternative and common use case in almost every EDA flow is simulation of post-compilation Verilog. ConstrainedRandom is intended for such a use case, and so the simulation tool must support it.

The request

In my case, I would like to take the output of the bsc compiler and simply read it, and needed modules such as ConstrainedRandom, into a design. I would then like to do two things:

write_verilog the output out to a sim.v file (after some preparation/massaging), which can then be read by Verilator, Icarus, etc or any simulator that supports $random today. While this feature isn't a strict necessity for me personally, it would be quite nice to have, and relatively trivial to do, I assume. There are probably similarly-useful standard tasks which could be "passed-thru" to write_verilog directly in this manner, but that's another discussion.
Simulate the design with cxxrtl backend, as well. This is what I really need in the long run, though it's much more complicated obviously. (In the mean time another simulator could be used, per point 1.)

In both cases, Yosys must at least support handling and generating a $random cell. However, this cell is firmly non-synthesizable, so the question of whether it should be supported is basically what we're here to figure out: what should the task "types" look like, if it should be supported at all?

Related: $display cells and other such stuff

A related issue is #2310 which is support for $display cells, which are also firmly non-synthesizable, but so useful as to merit support anyway, at least for a limited number of backends. So we might ask, are $random cells that useful too, or perhaps easy enough to support that it wouldn't be a burden?

Alternative: blackbox tasks in cxxrtl?

Even if write_verilog didn't support it, this would all be manageable on my part, if only I could simulate actual tasks in cxxrtl. But I don't think this is possible at all as it stands today, and I have no idea what the complexity/performance impact of such a feature would be on the backend overall. What you can do is use a non-standard module definition, blackbox it, and instantiate it at every use site, but this is obviously very cumbersome and doesn't work with pre-written code you can't change. I figured I would just mention this as something I thought about while doing a workaround.

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