About being killed when using yosys synthesis

kangliyu1 commented 2 years ago

Hello! When using script 1 to synthesize code1, there was a problem of being killed in the MEMORY_MAP step of synth. As shown in Figure 1, code1 can be synthesized normally in vivado. I feel very confused about this. I hope someone can give me some pointers. Thank you very much! ! Since there are many problems in the process of using yosys for synthesis, I also want to ask a question: What are the restrictions in the process of using yosys, for example, is there any code in code1 that yosys does not support? script 1：

read_verilog /home/kly/OpenFPGA/openfpga_flow/tasks/benchmark_sweep/mac_units_2/kly_test/Conv_3.v
hierarchy -top Conv_3
proc
techmap -D NO_LUT -map /home/kly/OpenFPGA/yosys/share/adff2dff.v
synth -top Conv_3 -flatten
clean
abc -lut 6
synth -run check
opt_clean -purge
write_blif Conv_3_yosys_out.blif

fig1：

code1:

`timescale 1ns / 1ps
module Conv_3#(
        parameter padding       =      0                                ,
        parameter weight_bit    =      10                               ,//鏈夌鍙蜂綅瀹?
        parameter conv_bit      =      10                               ,//鏃犵鍙蜂綅瀹?
        parameter conv_wid      =      10                               ,
        parameter conv_heig     =      10                              ,
        parameter stride        =      1                                ,
        parameter result_len    =      8*8                            ,
        parameter in_layer      =      16                                ,
        parameter out_layer     =      16                                
)(
        input                                                                           clk             ,
        input                                                                           rst             ,
        input           [159:0]                                         conv_din        ,
        input                                                                           din_vld         ,
        input                                                                           din_last        ,
        input           [0:1439]                                   kernel          ,
        output          [3071:0]              conv_dout       ,
        output                                                                          busy            ,
        output          [4:0]                                         kernel_addr     ,
        output  reg                                                                     kernel_vld      ,
        output  reg                                                                     dout_vld        ,
        output  reg                                                                     dout_last       

    );
        localparam rd_init1              =   3'b000       ,
                   rd_init2              =   3'b001       ,
                   rd_init3              =   3'b010       ,
                   rd_conv               =   3'b011       ; 
        reg     signed  [23:0]   add_res   [0:7][0:15]                 ;
        reg     signed  [19:0]     mul_res   [0:7][0:15][0:9-1]          ;  
        wire    signed  [9:0]              kernel_val[0:71]                            ;
        reg     signed  [10:0]                  conv_buf  [0:2-1][0:7][0:9-1]                  ;        
        wire            [159:0]       row_out   [0:3-1]                                           ;             
        wire            [159:0]       row_in    [0:3-1]                                           ;      
        reg     [9:0]                         cnt_row0                          ;       
        reg     [9:0]                         cnt_row1                          ;       
        reg     [9:0]                         cnt_row2                          ;           
        wire    [2:0]                         row_wr                            ;
        wire    [2:0]                         row_rd                            ;
        reg     [1:0]                         cnt_stride_w                      ;
        reg     [1:0]                         cnt_stride_h                      ;
        reg                                   row0_rd                           ;
        reg                                   row1_rd                           ;
        reg                                   row2_rd                           ;
        reg                                   conv_idle                         ;
        reg                                   conv_vld                          ;
        reg                                   last_vld                          ;
        reg     [3:0]        cnt_conv                       ;
        reg     [4:0]       cnt_kernel                          ;
        reg     [1:0]               cnt_paral                       ;
        wire    [2:0]                         row_full                          ;
        wire    [2:0]                         row_empty                         ;
        reg     [19:0]                        cnt_din                           ;
        reg     [2:0]                         state_rd                          ;
        reg     [0:0]                         row1_add_flag                     ;
        reg     [0:0]                         row0_add_flag                     ;
        reg     [6:0]      cnt_out                          ;

        wire end_din,conv_rst,add_din,add_kernel,end_kernel,add_paral,end_paral,add_conv,end_conv;
        wire init1_init2,add_stride_h,end_stride_h,add_stride_w,end_stride_w;
        wire init2_init3,add_out,end_out,add_row2,end_row2,add_row1,end_row1,add_row0,end_row0;
        wire init3_conv ;
        wire conv_init1 ;

        genvar                  a, b, c, i, j, k, l, m, n, o                    ;
        assign conv_rst         =   din_last && din_vld && !end_din || rst      ;
        assign row_wr[2]        =   din_vld && !row_full[2]                     ;
        assign row_rd[2]        =   !row_empty[2] && row2_rd                    ;
        assign row_in[2]        =   conv_din                                    ;
        assign row_wr[1]        =   row_rd[2] && !row_full[1]                   ;
        assign row_in[1]        =   row_out[2]                                  ;
        assign row_wr[0]        =   row_rd[1] && !row_full[0]                   ;
        assign row_in[0]        =   row_out[1]                                  ;
        assign row_rd[0]        =   !row_empty[0] && row0_rd                    ;
        assign row_rd[1]        =   !row_empty[1] && row1_rd                    ;
        assign busy             =   row_full[2]                                 ;
        assign kernel_addr      =   cnt_kernel                                  ;
        always@(posedge clk)begin
            if(conv_rst) 
                state_rd <= rd_init1;
            else
            case(state_rd)
            rd_init1:
                if(init1_init2)
                    state_rd <= rd_init2;
            rd_init2:
                if(init2_init3)
                    state_rd <= rd_init3;
            rd_init3:
                if(init3_conv)
                    state_rd <= rd_conv;
            rd_conv:
                if(conv_init1)
                    state_rd <= rd_init1;
            default:state_rd <= rd_init1;
            endcase
        end
        assign init1_init2      =   state_rd == rd_init1 && row_empty[1]                                    ;
        assign init2_init3      =   state_rd == rd_init2 && row_empty[0]                                    ;
        assign init3_conv       =   state_rd == rd_init3 && cnt_row2 == conv_wid*2 && cnt_row1 == conv_wid  ;
        assign conv_init1       =   state_rd == rd_conv &&  end_row2                                        ;
       generate 
            for(o=0;o<2;o=o+1) begin
                for(a=0;a<in_layer/2;a=a+1) begin 
                    for(i=0;i<3;i=i+1) begin 
                      for (j=0;j<3;j=j+1) begin
                        if(j == 2)begin:assignment
                          always@(posedge clk)begin
                            if(conv_rst) 
                              conv_buf[o][a][i*3+2] <= 'd0;
                            else
                            if(add_conv) 
                              conv_buf[o][a][i*3+2] <= {1'b0, row_out[i][(o*8+a)*10+:10]}; 
                          end 
                        end
                        else begin:shift    
                          always@(posedge clk)begin
                            if(conv_rst) 
                              conv_buf[o][a][i*3+j] <= 'd0;
                            else
                            if(add_conv) 
                              conv_buf[o][a][i*3+j] <= conv_buf[o][a][i*3+j+1];  
                          end 
                        end
                      end
                    end
                end
            end
        endgenerate
        integer n1,b1,k1;
        generate 
         always@(posedge clk)begin
            for(n1=0;n1<1;n1=n1+1)begin 
                for(b1=0;b1<in_layer/2;b1=b1+1)begin 
                    for(k1=0;k1<9;k1=k1+1)begin  
                         //kernel_val[n1*in_layer*9+b1*9+k1] = kernel[(cnt_paral*in_layer/2*9+n1*in_layer*9+b1*9+k1)*weight_bit+:weight_bit];
                        if(conv_bit != 1'b1)begin:mul

                                mul_res[b1][cnt_kernel+out_layer/1*n1][k1] <= kernel_val[n1*in_layer*9+b1*9+k1] * conv_buf[cnt_paral][b1][k1];
                            end
                        end
                    end
                end
            end
        endgenerate

                genvar n2,b2,k2;
   generate

         for(n2=0;n2<1;n2=n2+1)begin 
           for(b2=0;b2<in_layer/2;b2=b2+1)begin 
                for(k2=0;k2<9;k2=k2+1)begin  
                      assign  kernel_val[n2*in_layer*9+b2*9+k2] = kernel[(cnt_paral*in_layer/2*9+n2*in_layer*9+b2*9+k2)*weight_bit+:weight_bit];

                end
            end
          end

          endgenerate

        generate         
            for(c=0;c<8;c=c+1)begin    
                for(l=0;l<16;l=l+1) begin 
                  always@(posedge clk)begin
                    if(conv_rst) 
                      add_res[c][l] <= 'd0;
                    else
                      add_res[c][l] <= mul_res[c][l][0]+mul_res[c][l][1]+mul_res[c][l][2]+mul_res[c][l][3]+mul_res[c][l][4]+mul_res[c][l][5]+mul_res[c][l][6]+mul_res[c][l][7]+mul_res[c][l][8];
                  end  

                  assign conv_dout[(c*out_layer+l)*(4+weight_bit+conv_bit)+:(4+weight_bit+conv_bit)] = add_res[c][l]        ;
                end
            end
        endgenerate
        always@(*)begin
            if(state_rd == rd_init1) begin
                row0_rd = 1'b1;
                row1_rd = 1'b1;
                row2_rd = 1'b0;                
            end
            else
            if(state_rd == rd_init2) begin
                row0_rd = 1'b1;
                row1_rd = 1'b0;
                row2_rd = cnt_row2 < conv_wid;                
            end
            else
            if(state_rd == rd_init3) begin
                row0_rd = 1'b0;
                row1_rd = cnt_row1 < conv_wid; 
                row2_rd = cnt_row2 < conv_wid * 2;                
            end
            else 
            if(state_rd == rd_conv && !row_empty[2] && conv_idle) begin
                row0_rd = 1'b1;
                row1_rd = 1'b1;
                row2_rd = 1'b1;                 
            end
            else begin
                row0_rd = 1'b0;
                row1_rd = 1'b0;
                row2_rd = 1'b0;                 
            end
        end

        always@(posedge clk)begin
            if(conv_rst) 
                conv_idle <= 1'b1;
            else
            if(state_rd == rd_conv)begin
                if(cnt_conv < 2 && !kernel_vld)
                    conv_idle <= 1'b1;
                else
                if(row_rd[2] && cnt_stride_w == 0 && cnt_stride_h == 0)
                    conv_idle <= 1'b0; 
                else
                if(end_paral)
                    conv_idle <= 1'b1;
            end
        end
        always@(posedge clk)begin
          if(conv_rst)
            cnt_din <= 20'd0;
          else
          if(end_din || din_last)
            cnt_din <= 10'd0;
          else
          if(add_din)
            cnt_din <= cnt_din + 1'b1;
        end
        assign  add_din =   row_wr[2]                                           ;
        assign  end_din =   add_din && cnt_din >= conv_wid * conv_heig - 1      ;
        always @(posedge clk ) begin
            if(conv_rst)
                row1_add_flag <= 1'b0;
            else
            if(state_rd == rd_init1 && row_empty[1])
                row1_add_flag <= 1'b1;
            else
            if(end_row2)
                row1_add_flag <= 1'b0;
        end
        always @(posedge clk ) begin
            if(conv_rst)
                row0_add_flag <= 1'b0;
            else
            if(state_rd == rd_init2 && row_empty[0])
                row0_add_flag <= 1'b1;
            else
            if(end_row2)
                row0_add_flag <= 1'b0;
        end

        always@(posedge clk)begin
            if(conv_rst)
                cnt_kernel <= 'd0;
            else
           if(end_kernel)
                cnt_kernel <= 'd0;
           else
           if(add_kernel)
                cnt_kernel <= cnt_kernel + 1'b1;
        end
        assign  add_kernel  =   kernel_vld                                                  ;
        assign  end_kernel  =   add_kernel && cnt_kernel >= out_layer / 1 - 1'b1    ;
        always@(posedge clk)begin
            if(conv_rst)
                cnt_paral <= 'd0;
            else
            if(end_paral)
                cnt_paral <= 'd0;
            else
            if(add_paral)
                cnt_paral <= cnt_paral + 1'b1;
        end
        assign  add_paral   =   end_kernel                                              ;
        assign  end_paral   =   add_paral && cnt_paral >= 2 - 1             ;
        always@(posedge clk)begin
            if(conv_rst)
                cnt_conv <= 'd0;
            else
            if(end_conv)
                cnt_conv <= 'd0;
            else
            if(add_conv)
                cnt_conv <= cnt_conv + 1'b1;
        end
        assign  add_conv    =   state_rd == rd_conv && row_rd[2]                        ;
        assign  end_conv    =   add_conv && cnt_conv >= conv_wid - 1'b1                 ;
        always@(posedge clk)begin
            if(conv_rst)
                cnt_stride_h <= 'd0;
            else
            if(end_stride_h || end_row2)
                cnt_stride_h <= 'd0;
            else
            if(add_stride_h)
                cnt_stride_h <= cnt_stride_h + 1'b1;
        end
        assign  add_stride_h    =   end_conv                                             ;
        assign  end_stride_h    =   add_stride_h && cnt_stride_h >= stride - 1'b1        ;
        always@(posedge clk)begin
            if(conv_rst)
                cnt_stride_w <= 'd0;
            else
            if(end_stride_w || (cnt_conv < 2))
                cnt_stride_w <= 'd0;
            else
            if(add_stride_w)
                cnt_stride_w <= cnt_stride_w + 1'b1;
        end
        assign  add_stride_w    =   add_conv && cnt_conv >= 2                             ;
        assign  end_stride_w    =   add_stride_w && cnt_stride_w >= stride - 1            ;

        always @(posedge clk ) begin
            if(conv_rst)begin
                conv_vld <= 1'b0;
                last_vld <= 1'b0;                
                dout_vld  <= 1'b0;
                dout_last <= 1'b0;
            end
            else begin
                conv_vld  <= end_kernel;
                last_vld <= end_out;
                dout_vld <= conv_vld;
                dout_last <= last_vld;
            end
        end
        always@(posedge clk)begin
            if(conv_rst)
                cnt_out <= 'd0;
            else
           if(end_out)
                cnt_out <= 'd0;
           else
           if(add_out)
                cnt_out <= cnt_out + 1'b1;
        end
        assign  add_out =   end_paral                           ;
        assign  end_out =   add_out && cnt_out >= result_len - 1;
        always@(posedge clk)begin
            if(conv_rst) 
                kernel_vld <= 1'b0;
            else
            if(add_stride_w && cnt_stride_w == 0 && cnt_stride_h == 0)
                kernel_vld <= 1'b1;    
            else
            if(end_paral)
                kernel_vld <= 1'b0;
        end
        always@(posedge clk)begin
            if(conv_rst)
                cnt_row2 <= 10'd0;
            else
            if(end_row2)
                cnt_row2 <= 10'd0;
            else
            if(add_row2)
                cnt_row2 <= cnt_row2 + 1'b1;
        end
        assign  add_row2    =   row_rd[2]                                                       ;
        assign  end_row2    =   add_row2 && cnt_row2 >= conv_wid * conv_heig - 1                ;
        always@(posedge clk)begin
            if(conv_rst)
                cnt_row1 <= 10'd0;
            else
            if(end_row1 || end_row2)
                cnt_row1 <= 10'd0;
            else
            if(add_row1)
                cnt_row1 <= cnt_row1 + 1'b1;
        end
        assign  add_row1    =   row_rd[1] && row1_add_flag                                      ;
        assign  end_row1    =   add_row1 && cnt_row1 >= conv_wid * conv_heig - 1 - conv_wid     ;
        always@(posedge clk)begin
            if(conv_rst)
                cnt_row0 <= 10'd0;
            else
            if(end_row0 || end_row2)
                cnt_row0 <= 10'd0;
            else
            if(add_row0)
                cnt_row0 <= cnt_row0 + 1'b1;
        end
        assign  add_row0    =   row_rd[0] && row0_add_flag                                      ;
        assign  end_row0    =   add_row0 && cnt_row0 >= conv_wid * conv_heig - 1 - conv_wid*2   ;       
        fifo FIFO_0(.clk(clk),
                        .rst_n(~conv_rst),
                         .din(row_in[0]),
                        . we(row_wr[0]),
                        . re(row_rd[0]),
                        . dout(row_out[0]),
                        .empty(row_full[0]),
                        . full(row_empty[0]));

          fifo FIFO_1(.clk(clk),
                        .rst_n(~conv_rst),
                         .din(row_in[1]),
                        . we(row_wr[1]),
                        . re(row_rd[1]),
                        . dout(row_out[1]),
                        .empty(row_full[1]),
                        . full(row_empty[1]));

         fifo FIFO_2(.clk(clk),
                        .rst_n(~conv_rst),
                         .din(row_in[2]),
                        . we(row_wr[2]),
                        . re(row_rd[2]),
                        . dout(row_out[2]),
                        .empty(row_full[2]),
                        . full(row_empty[2]));          

            //end
        //endgenerate
        /*function integer clogb2;
          input integer depth;
            for (clogb2=0; depth>0; clogb2=clogb2+1)
              depth = depth >> 1;
        endfunction*/
endmodule

module fifo
#(parameter DW = 160,AW = 9)//默认数据宽度8，FIFO深度16
(
    input clk,
    input rst_n,
    input we,
    input re,
    input [DW-1:0]din,
    output reg [DW-1:0]dout,
    output empty,
    output full
    );
// internal signal
parameter Depth = 1 << AW;//depth of FIFO 
reg [DW-1:0]ram[0:Depth-1];
reg [AW:0]cnt;
reg [AW-1:0]wp;
reg [AW-1:0]rp;
// FIFO declaration
// 空满检测
assign empty = (cnt==0)?1'b1:1'b0;
assign full = (cnt==Depth)?1'b1:1'b0;
// cnt 计数
always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        cnt <= 1'd0;
    else if(!empty & re & !full & we)//同时读写
        cnt <= cnt;
    else if(!full & we)//写
        cnt <= cnt+1;
    else if(!empty & re)//读
        cnt <= cnt-1;
    else 
        cnt <= cnt;
end
// 读指针
always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        rp <= 1'b0;
    else if(!empty & re)
        rp <= rp+1'b1;
    else
        rp <= rp;
end
//写指针
always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        wp <= 1'b0;
    else if(!full & we)
        wp <= wp+1'b1;
    else
        wp <= wp;
end
// 读操作
always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        dout <= {DW{1'b0}};
    else if(!empty & re)
        dout <= ram[rp];
    else
        dout <= dout;
end
//写操作
always@(posedge clk)
begin
    if(!full & we)
        ram[wp] <= din;
    else
        ram[wp] <= ram[wp];
end
endmodule

Ravenslofty commented 2 years ago

Though I don't feel like running a test to check, my suspicion is that because you're not invoking memory_bram to turn memories into block RAMs, you're instead turning the whole thing into DFF RAM, and in this case the memory is so big that Yosys runs out of memory trying to map it.

kangliyu1 commented 2 years ago

Though I don't feel like running a test to check, my suspicion is that because you're not invoking memory_bram to turn memories into block RAMs, you're instead turning the whole thing into DFF RAM, and in this case the memory is so big that Yosys runs out of memory trying to map it.

Thank you very much for your reply, hello! When I use the script 1 below to synthesize the same Conv_3.v, it is still "killed" as shown in Figure 1. It is interrupted at the stage of "24.2. Continuing TECHMAP pass." The script below contains the memory_bram you mentioned, but It is still interrupted, and I am very confused about this. No one has replied to me before, so I am sorry for not adding any questions. I hope you can give me some pointers, thank you very much! !

scripts1：

# Yosys synthesis script for Conv_3
#########################
# Parse input files
#########################
# Read verilog files
read_verilog -nolatches ./benchmark/Conv_3.v
# Read technology library
read_verilog -lib -specify /home/kly/OpenFPGA/openfpga_flow/tasks/benchmark_sweep/mac_units/a_file/yosys_file/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v
#########################
# Prepare for synthesis
#########################
# Identify top module from hierarchy
hierarchy -check -top Conv_3
# - Convert process blocks to AST
proc
# Flatten all the gates/primitives
flatten
# Identify tri-state buffers from 'z' signal in AST
# with follow-up optimizations to clean up AST
tribuf -logic
opt_expr
opt_clean
# demote inout ports to input or output port
# with follow-up optimizations to clean up AST
deminout
opt
opt_expr
opt_clean
check
opt
wreduce -keepdc
peepopt
pmuxtree
opt_clean
########################
# Map multipliers
# Inspired from synth_xilinx.cc
#########################
# Avoid merging any registers into DSP, reserve memory port registers first
memory_dff
wreduce t:$mul
techmap -map /home/kly/OpenFPGA/yosys/share/mul2dsp.v -map /home/kly/OpenFPGA/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v -D DSP_A_MAXWIDTH=36 -D DSP_B_MAXWIDTH=36 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_36x36
select a:mul2dsp
setattr -unset mul2dsp
opt_expr -fine
wreduce
select -clear
chtype -set $mul t:$__soft_mul# Extract arithmetic functions
#########################
# Run coarse synthesis
#########################
# Run a tech map with default library
techmap
alumacc
share
opt
fsm
# Run a quick follow-up optimization to sweep out unused nets/signals
opt -fast
# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells  
memory -nomap
opt_clean
#########################
# Map logics to BRAMs
#########################
memory_bram -rules /home/kly/OpenFPGA/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt
techmap -map /home/kly/OpenFPGA/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v
opt -fast -mux_undef -undriven -fine
memory_map
opt -undriven -fine
#########################
# Map flip-flops
#########################
techmap -map /home/kly/OpenFPGA/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v
opt_expr -mux_undef
simplemap
opt_expr
opt_merge
opt_rmdff
opt_clean
opt
#########################
# Map LUTs
#########################
abc -lut 6
#########################
# Check and show statisitics
#########################
hierarchy -check
stat
#########################
# Output netlists
#########################
opt_clean -purge
write_blif Conv_3_yosys_out.blif

log1:

24.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $logic_and.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $logic_or.
Using extmapper simplemap for cells of type $eq.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=6:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=7:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=6:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=7:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=6:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=7:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=7:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=7:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=7:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$lt:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$lt:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$lt:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$lt:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$lt:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$lt:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$lt:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$lt:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$lt:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=20:B_SIGNED=0:B_WIDTH=7:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=20:B_SIGNED=0:B_WIDTH=7:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=20:B_SIGNED=0:B_WIDTH=7:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=20:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=20:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=20:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=20:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=20:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=20:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=5:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=5:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=5:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=4:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=4:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=4:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=7:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=7:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=7:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=7:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=7:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=7:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=7:B_SIGNED=0:B_WIDTH=6:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=7:B_SIGNED=0:B_WIDTH=6:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=7:B_SIGNED=0:B_WIDTH=6:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=7:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=7:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=7:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $adff.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=9:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=9:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=9:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Using extmapper simplemap for cells of type $and.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=1:A_WIDTH=20:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=21:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=1:A_WIDTH=20:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=21:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=1:A_WIDTH=20:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=21:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=1:A_WIDTH=21:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=22:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=1:A_WIDTH=21:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=22:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=1:A_WIDTH=21:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=22:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=1:A_WIDTH=22:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=23:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=1:A_WIDTH=22:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=23:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=1:A_WIDTH=22:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=23:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=1:A_WIDTH=23:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=24:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=1:A_WIDTH=23:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=24:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=1:A_WIDTH=23:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=24:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=1:A_WIDTH=24:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=24:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=1:A_WIDTH=24:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=24:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=1:A_WIDTH=24:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=24:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=13:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=13:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=13:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $paramod$constmap:d97e6990a6cfa5c249c8bf332be3c42382b3cfe5$paramod$700df59ac3d2026373a22ae5e0cc18ceaf240a56\_90_shift_shiftx for cells of type $shiftx.
Running "alumacc" on wrapper $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=14:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=14:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=14:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=15:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=15:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=15:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=6:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=6:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=6:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=11\B_WIDTH=14\Y_WIDTH=32 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=9\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=10\Y_WIDTH=11 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=10\Y_WIDTH=11 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=11\B_WIDTH=15\Y_WIDTH=32 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=10\Y_WIDTH=11 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=10\Y_WIDTH=11 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=9\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=6\B_WIDTH=9\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=9\Y_WIDTH=9 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=1\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=9\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=9\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=9\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=5\Y_WIDTH=6 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=6 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=5\Y_WIDTH=6 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=6\Y_WIDTH=7 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=11\Y_WIDTH=11 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=11\Y_WIDTH=11 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=11\Y_WIDTH=11 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=11\Y_WIDTH=11 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=5\Y_WIDTH=6 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=7\Y_WIDTH=8 for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_and.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=7\B_WIDTH=20\Y_WIDTH=20 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=20\Y_WIDTH=20 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=7\Y_WIDTH=7 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=6\B_WIDTH=7\Y_WIDTH=7 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=7\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=1\B_SIGNED=1\A_WIDTH=20\B_WIDTH=20\Y_WIDTH=21 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=1\B_SIGNED=1\A_WIDTH=20\B_WIDTH=21\Y_WIDTH=22 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=1\B_SIGNED=1\A_WIDTH=20\B_WIDTH=22\Y_WIDTH=23 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=1\B_SIGNED=1\A_WIDTH=20\B_WIDTH=23\Y_WIDTH=24 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=1\B_SIGNED=1\A_WIDTH=20\B_WIDTH=24\Y_WIDTH=24 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=11\B_WIDTH=13\Y_WIDTH=32 for cells of type $alu.
Killed

Tanvir-Rizve commented 9 months ago

Have you got any solution for this problem?

Though I don't feel like running a test to check, my suspicion is that because you're not invoking memory_bram to turn memories into block RAMs, you're instead turning the whole thing into DFF RAM, and in this case the memory is so big that Yosys runs out of memory trying to map it.

Thank you very much for your reply, hello! When I use the script 1 below to synthesize the same Conv_3.v, it is still "killed" as shown in Figure 1. It is interrupted at the stage of "24.2. Continuing TECHMAP pass." The script below contains the memory_bram you mentioned, but It is still interrupted, and I am very confused about this. No one has replied to me before, so I am sorry for not adding any questions. I hope you can give me some pointers, thank you very much! !

scripts1：

# Yosys synthesis script for Conv_3
#########################
# Parse input files
#########################
# Read verilog files
read_verilog -nolatches ./benchmark/Conv_3.v
# Read technology library
read_verilog -lib -specify /home/kly/OpenFPGA/openfpga_flow/tasks/benchmark_sweep/mac_units/a_file/yosys_file/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v
#########################
# Prepare for synthesis
#########################
# Identify top module from hierarchy
hierarchy -check -top Conv_3
# - Convert process blocks to AST
proc
# Flatten all the gates/primitives
flatten
# Identify tri-state buffers from 'z' signal in AST
# with follow-up optimizations to clean up AST
tribuf -logic
opt_expr
opt_clean
# demote inout ports to input or output port
# with follow-up optimizations to clean up AST
deminout
opt
opt_expr
opt_clean
check
opt
wreduce -keepdc
peepopt
pmuxtree
opt_clean
########################
# Map multipliers
# Inspired from synth_xilinx.cc
#########################
# Avoid merging any registers into DSP, reserve memory port registers first
memory_dff
wreduce t:$mul
techmap -map /home/kly/OpenFPGA/yosys/share/mul2dsp.v -map /home/kly/OpenFPGA/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v -D DSP_A_MAXWIDTH=36 -D DSP_B_MAXWIDTH=36 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_36x36
select a:mul2dsp
setattr -unset mul2dsp
opt_expr -fine
wreduce
select -clear
chtype -set $mul t:$__soft_mul# Extract arithmetic functions
#########################
# Run coarse synthesis
#########################
# Run a tech map with default library
techmap
alumacc
share
opt
fsm
# Run a quick follow-up optimization to sweep out unused nets/signals
opt -fast
# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells  
memory -nomap
opt_clean
#########################
# Map logics to BRAMs
#########################
memory_bram -rules /home/kly/OpenFPGA/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt
techmap -map /home/kly/OpenFPGA/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v
opt -fast -mux_undef -undriven -fine
memory_map
opt -undriven -fine
#########################
# Map flip-flops
#########################
techmap -map /home/kly/OpenFPGA/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v
opt_expr -mux_undef
simplemap
opt_expr
opt_merge
opt_rmdff
opt_clean
opt
#########################
# Map LUTs
#########################
abc -lut 6
#########################
# Check and show statisitics
#########################
hierarchy -check
stat
#########################
# Output netlists
#########################
opt_clean -purge
write_blif Conv_3_yosys_out.blif

log1:

24.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $logic_and.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $logic_or.
Using extmapper simplemap for cells of type $eq.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=6:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=7:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=6:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=7:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=6:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=7:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=11:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=7:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=7:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=7:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$lt:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$lt:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$lt:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$lt:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$lt:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$lt:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$lt:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$lt:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$lt:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=20:B_SIGNED=0:B_WIDTH=7:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=20:B_SIGNED=0:B_WIDTH=7:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=20:B_SIGNED=0:B_WIDTH=7:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=20:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=20:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=20:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=20:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=20:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=20:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=5:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=5:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=5:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=4:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=4:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=4:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=7:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=7:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=7:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=7:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=7:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=7:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=7:B_SIGNED=0:B_WIDTH=6:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=7:B_SIGNED=0:B_WIDTH=6:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=7:B_SIGNED=0:B_WIDTH=6:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=7:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=7:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=7:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $adff.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=9:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=9:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=9:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Using extmapper simplemap for cells of type $and.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=1:A_WIDTH=20:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=21:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=1:A_WIDTH=20:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=21:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=1:A_WIDTH=20:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=21:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=1:A_WIDTH=21:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=22:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=1:A_WIDTH=21:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=22:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=1:A_WIDTH=21:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=22:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=1:A_WIDTH=22:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=23:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=1:A_WIDTH=22:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=23:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=1:A_WIDTH=22:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=23:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=1:A_WIDTH=23:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=24:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=1:A_WIDTH=23:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=24:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=1:A_WIDTH=23:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=24:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=1:A_WIDTH=24:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=24:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=1:A_WIDTH=24:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=24:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=1:A_WIDTH=24:B_SIGNED=1:B_WIDTH=20:Y_WIDTH=24:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=13:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=13:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=13:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $paramod$constmap:d97e6990a6cfa5c249c8bf332be3c42382b3cfe5$paramod$700df59ac3d2026373a22ae5e0cc18ceaf240a56\_90_shift_shiftx for cells of type $shiftx.
Running "alumacc" on wrapper $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=14:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=14:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=14:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=15:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=15:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=11:B_SIGNED=0:B_WIDTH=15:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=6:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=6:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=6:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=11\B_WIDTH=14\Y_WIDTH=32 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=9\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=10\Y_WIDTH=11 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=10\Y_WIDTH=11 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=11\B_WIDTH=15\Y_WIDTH=32 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=10\Y_WIDTH=11 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=10\Y_WIDTH=11 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=9\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=6\B_WIDTH=9\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=9\Y_WIDTH=9 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=1\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=9\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=9\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=9\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=5\Y_WIDTH=6 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=6 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=5\Y_WIDTH=6 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=6\Y_WIDTH=7 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=11\Y_WIDTH=11 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=11\Y_WIDTH=11 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=11\Y_WIDTH=11 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=11\Y_WIDTH=11 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=5\Y_WIDTH=6 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=7\Y_WIDTH=8 for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_and.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=7\B_WIDTH=20\Y_WIDTH=20 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=20\Y_WIDTH=20 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=7\Y_WIDTH=7 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=6\B_WIDTH=7\Y_WIDTH=7 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=7\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=1\B_SIGNED=1\A_WIDTH=20\B_WIDTH=20\Y_WIDTH=21 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=1\B_SIGNED=1\A_WIDTH=20\B_WIDTH=21\Y_WIDTH=22 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=1\B_SIGNED=1\A_WIDTH=20\B_WIDTH=22\Y_WIDTH=23 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=1\B_SIGNED=1\A_WIDTH=20\B_WIDTH=23\Y_WIDTH=24 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=1\B_SIGNED=1\A_WIDTH=20\B_WIDTH=24\Y_WIDTH=24 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=11\B_WIDTH=13\Y_WIDTH=32 for cells of type $alu.
Killed

YosysHQ / yosys

About being killed when using yosys synthesis #3147