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Yosys Open SYnthesis Suite
https://yosyshq.net/yosys/
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Errors are printed during testsuite #3580

Closed yurivict closed 1 year ago

yurivict commented 1 year ago

Version

0.24

On which OS did this happen?

BSD

Reproduction Steps

make test

Expected Behavior

n/a

Actual Behavior

Running from a child directory with content2.dat
Checking a failure when zero length filename is provided
memory.v:0: ERROR: Can not open file `` for \$readmemb.
Execution failed, which is OK.
Checking a failure when not existing filename is provided
memory.v:0: ERROR: Can not open file `content3.dat` for \$readmemb.
Execution failed, which is OK.
cd tests/verilog && bash run-test.sh
gmake[2]: Entering directory '/disk-samsung/freebsd-ports/cad/yosys/work/yosys-yosys-0.24/tests/verilog'
<<EOF:0: ERROR: Expression width 1073741824 exceeds implementation limit of 16777216!
Expected error pattern 'Expression width 1073741824 exceeds implementation limit of 16777216!' found !!!
Passed absurd_width.ys
<<EOF:0: ERROR: Expression width 1073741824 exceeds implementation limit of 16777216!
Expected error pattern 'Expression width 1073741824 exceeds implementation limit of 16777216!' found !!!
Passed absurd_width_const.ys
ERROR: Latch inferred for signal `\top.$unnamed_block$1.y' from always_comb process `\top.$proc$<<EOF:0$2'.
Expected error pattern '^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process' found !!!
Passed always_comb_latch_1.ys
ERROR: Latch inferred for signal `\top.$unnamed_block$1.y' from always_comb process `\top.$proc$<<EOF:0$2'.
Expected error pattern '^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process' found !!!
Passed always_comb_latch_2.ys
ERROR: Latch inferred for signal `\top.$unnamed_block$1.y' from always_comb process `\top.$proc$<<EOF:0$2'.
Expected error pattern '^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process' found !!!
Passed always_comb_latch_3.ys
ERROR: Latch inferred for signal `\top.$unnamed_block$3.y' from always_comb process `\top.$proc$<<EOF:0$4'.
Expected error pattern '^Latch inferred for signal `\\top\.\$unnamed_block\$3\.y' from always_comb process' found !!!
Passed always_comb_latch_4.ys
Passed always_comb_nolatch_1.ys
Passed always_comb_nolatch_2.ys
Passed always_comb_nolatch_3.ys
Passed always_comb_nolatch_4.ys
Passed always_comb_nolatch_5.ys
Passed always_comb_nolatch_6.ys
Passed atom_type_signedness.ys
<<EOF:5: ERROR: Begin label missing where end label (incorrect_name) was given.
Expected error pattern 'Begin label missing where end label \(incorrect_name\) was given\.' found !!!
Passed block_end_label_only.ys
<<EOF:5: ERROR: Begin label (correct_name) and end label (incorrect_name) don't match.
Expected error pattern 'Begin label \(correct_name\) and end label \(incorrect_name\) don't match\.' found !!!
Passed block_end_label_wrong.ys
<<EOT:5: ERROR: Begin label (a) and end label (b) don't match.
Expected error pattern 'Begin label \(a\) and end label \(b\) don't match\.' found !!!
Passed block_labels.ys
Passed bug2037.ys
<<EOT:6: ERROR: syntax error, unexpected TOK_ENDTASK, expecting ';'
Expected error pattern 'syntax error, unexpected TOK_ENDTASK, expecting ';'' found !!!
Passed bug2042-sv.ys
<<EOT:5: ERROR: task/function argument direction missing
Expected error pattern 'task/function argument direction missing' found !!!
Passed bug2042.ys
<<EOT:6: ERROR: Failed to detect width for identifier \genblk1.y!
Expected error pattern 'Failed to detect width for identifier \\genblk1\.y!' found !!!
Passed bug2493.ys
Passed bug656.ys
<<EOT:4: ERROR: Cannot add procedural assertion `\x' because a signal with the same name was already created at <<EOT:2.10-2.11!
Expected error pattern 'Cannot add procedural assertion `\\x' because a signal with the same name was already created' found !!!
Passed conflict_assert.ys
<<EOT:5: ERROR: Cannot add cell `\x' because a memory with the same name was already created at <<EOT:4.15-4.16!
Expected error pattern 'Cannot add cell `\\x' because a memory with the same name was already created' found !!!
Passed conflict_cell_memory.ys
<<EOT:0: ERROR: Cannot add interface port `\i' because a signal with the same name was already created at <<EOT:9.10-9.11!
Expected error pattern 'Cannot add interface port `\\i' because a signal with the same name was already created' found !!!
Passed conflict_interface_port.ys
<<EOT:3: ERROR: Cannot add memory `\x' because a signal with the same name was already created at <<EOT:2.15-2.16!
Expected error pattern 'Cannot add memory `\\x' because a signal with the same name was already created' found !!!
Passed conflict_memory_wire.ys
<<EOT:3: Warning: Ignoring assignment to constant bits:
    old assignment: 2 = 1
    new assignment: { } = { }.
<<EOT:4: ERROR: Cannot add pwire `\x' because a signal with the same name was already created at <<EOT:2.10-2.11!
Expected error pattern 'Cannot add pwire `\\x' because a signal with the same name was already created' found !!!
Passed conflict_pwire.ys
<<EOT:3: ERROR: Cannot add signal `\x' because a memory with the same name was already created at <<EOT:2.15-2.16!
Expected error pattern 'Cannot add signal `\\x' because a memory with the same name was already created' found !!!
Passed conflict_wire_memory.ys
Passed const_arst.ys
Warning: Complex async reset for dff `\q'.
Passed const_sr.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:3)
Passed delay_mintypmax.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:3)
Passed delay_risefall.ys
Passed delay_time_scale.ys
Passed doubleslash.ys
<<EOT:4: ERROR: For loop variable declaration is missing initialization!
Expected error pattern 'For loop variable declaration is missing initialization!' found !!!
Passed for_decl_no_init.ys
<<EOT:4: ERROR: For loop inline variable declaration is only supported in SystemVerilog mode!
Expected error pattern 'For loop inline variable declaration is only supported in SystemVerilog mode!' found !!!
Passed for_decl_no_sv.ys
Passed for_decl_shadow.ys
<<EOT:8: ERROR: Incompatible re-declaration of wire \f$func$<<EOT:8$1.inp.
Expected error pattern 'Incompatible re-declaration of wire' found !!!
Passed func_arg_mismatch_1.ys
<<EOT:0: ERROR: Incompatible re-declaration of constant function wire \f$func$<<EOT:8$1.inp.
Expected error pattern 'Incompatible re-declaration of constant function wire' found !!!
Passed func_arg_mismatch_2.ys
<<EOT:8: ERROR: Incompatible re-declaration of wire \f$func$<<EOT:8$1.inp.
Expected error pattern 'Incompatible re-declaration of wire' found !!!
Passed func_arg_mismatch_3.ys
<<EOT:0: ERROR: Incompatible re-declaration of constant function wire \f$func$<<EOT:8$1.inp.
Expected error pattern 'Incompatible re-declaration of constant function wire' found !!!
Passed func_arg_mismatch_4.ys
Passed func_tern_hint.ys
Passed func_typename_ret.ys
Passed func_upto.ys
<<EOF:5: ERROR: Begin label missing where end label (incorrect_name) was given.
Expected error pattern 'Begin label missing where end label \(incorrect_name\) was given\.' found !!!
Passed gen_block_end_label_only.ys
<<EOF:5: ERROR: Begin label (correct_name) and end label (incorrect_name) don't match.
Expected error pattern 'Begin label \(correct_name\) and end label \(incorrect_name\) don't match\.' found !!!
Passed gen_block_end_label_wrong.ys
Passed genblk_case.ys
<<EOT:4: ERROR: Cannot declare module port `\x' within a generate block.
Expected error pattern 'Cannot declare module port `\\x' within a generate block\.' found !!!
Passed genblk_port_decl.ys
<<EOT:2: ERROR: Generate for loop variable declaration is missing initialization!
Expected error pattern 'Generate for loop variable declaration is missing initialization!' found !!!
Passed genfor_decl_no_init.ys
<<EOT:2: ERROR: Generate for loop inline variable declaration is only supported in SystemVerilog mode!
Expected error pattern 'Generate for loop inline variable declaration is only supported in SystemVerilog mode!' found !!!
Passed genfor_decl_no_sv.ys
Passed genvar_loop_decl_1.ys
Passed genvar_loop_decl_2.ys
Warning: reg '\y' is assigned in a continuous assignment at genvar_loop_decl_3.sv:13.12-13.21.
Warning: reg '\y' is assigned in a continuous assignment at genvar_loop_decl_3.sv:27.12-27.21.
Passed genvar_loop_decl_3.ys
<<EOF:0: ERROR: Can't find object for defparam `$1`!
Expected error pattern 'Can't find object for defparam' found !!!
Passed global_parameter.ys
<<EOT:7: ERROR: Identifier `\y' is implicitly declared and `default_nettype is set to none.
Expected error pattern 'Identifier `\\y' is implicitly declared and `default_nettype is set to none' found !!!
Passed hidden_decl.ys
Passed ifdef_nest.ys
ERROR: Unterminated preprocessor conditional!
Expected error pattern 'Unterminated preprocessor conditional!' found !!!
Passed ifdef_unterminated.ys
Passed include_self.ys
Passed int_types.ys
<<EOF:3: ERROR: localparam initialization is missing!
Expected error pattern 'localparam initialization is missing!' found !!!
Passed localparam_no_default_1.ys
<<EOF:2: ERROR: localparam initialization is missing!
Expected error pattern 'localparam initialization is missing!' found !!!
Passed localparam_no_default_2.ys
Passed macro_arg_tromp.ys
ERROR: Expected to find '(' to begin macro arguments for 'MACRO', but instead found ';'
Expected error pattern 'Expected to find '\(' to begin macro arguments for 'MACRO', but instead found ';'' found !!!
Passed macro_unapplied.ys
ERROR: Expected to find '(' to begin macro arguments for 'foo', but instead found '\x0a'
Expected error pattern 'Expected to find '\(' to begin macro arguments for 'foo', but instead found '\\x0a'' found !!!
Passed macro_unapplied_newline.ys
Passed mem_bounds.ys
<<EOF:3: ERROR: Module name (correct_name) and end label (incorrect_name) don't match.
Expected error pattern 'Module name \(correct_name\) and end label \(incorrect_name\) don't match\.' found !!!
Passed module_end_label.ys
Passed net_types.ys
<<EOF:3: ERROR: Package name (correct_name) and end label (incorrect_name) don't match.
Expected error pattern 'Package name \(correct_name\) and end label \(incorrect_name\) don't match\.' found !!!
Passed package_end_label.ys
Passed package_task_func.ys
Passed param_int_types.ys
Passed param_no_default.ys
<<EOF:3: ERROR: Parameter defaults can only be omitted in SystemVerilog mode!
Expected error pattern 'Parameter defaults can only be omitted in SystemVerilog mode!' found !!!
Passed param_no_default_not_svmode.ys
<<EOF:2: ERROR: Parameter `\X' has no default value and has not been overridden!
Expected error pattern 'Parameter `\\X' has no default value and has not been overridden!' found !!!
Passed param_no_default_unbound_1.ys
<<EOF:2: ERROR: Parameter `\X' has no default value and has not been overridden!
Expected error pattern 'Parameter `\\X' has no default value and has not been overridden!' found !!!
Passed param_no_default_unbound_2.ys
<<EOF:2: ERROR: Parameter `\Y' has no default value and has not been overridden!
Expected error pattern 'Parameter `\\Y' has no default value and has not been overridden!' found !!!
Passed param_no_default_unbound_3.ys
<<EOF:2: ERROR: Parameter `\X' has no default value and has not been overridden!
Expected error pattern 'Parameter `\\X' has no default value and has not been overridden!' found !!!
Passed param_no_default_unbound_4.ys
<<EOF:2: ERROR: Parameter `\X' has no default value and has not been overridden!
Expected error pattern 'Parameter `\\X' has no default value and has not been overridden!' found !!!
Passed param_no_default_unbound_5.ys
Passed parameters_across_files.ys
Passed past_signedness.ys
Passed port_int_types.ys
Passed prefix.ys
Passed sign_array_query.ys
Passed size_cast.ys
Passed struct_access.ys
<<EOT:6: ERROR: syntax error, unexpected ATTR_BEGIN
Expected error pattern 'syntax error, unexpected ATTR_BEGIN' found !!!
Passed task_attr.ys
Passed typedef_across_files.ys
Passed typedef_legacy_conflict.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:17)
Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:21)
Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:25)
Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:30)
Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:34)
Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:38)
Passed unbased_unsized.ys
Warning: Resizing cell port gate.pt4.out from 64 bits to 40 bits.
Warning: Resizing cell port gate.pt3.out from 64 bits to 40 bits.
Warning: Resizing cell port gate.pt2.out from 64 bits to 40 bits.
Warning: Resizing cell port gate.pt1.out from 64 bits to 40 bits.
Warning: Resizing cell port gold.pt4.out from 64 bits to 40 bits.
Warning: Resizing cell port gold.pt3.out from 64 bits to 40 bits.
Warning: Resizing cell port gold.pt2.out from 64 bits to 40 bits.
Warning: Resizing cell port gold.pt1.out from 64 bits to 40 bits.
Passed unbased_unsized_tern.ys
ERROR: Found `else outside of macro conditional branch!
Expected error pattern 'Found `else outside of macro conditional branch!' found !!!
Passed unmatched_else.ys
ERROR: Found `elsif outside of macro conditional branch!
Expected error pattern 'Found `elsif outside of macro conditional branch!' found !!!
Passed unmatched_elsif.ys
ERROR: Found `endif outside of macro conditional branch!
Expected error pattern 'Found `endif outside of macro conditional branch!' found !!!
Passed unmatched_endif.ys
ERROR: Found `endif outside of macro conditional branch!
Expected error pattern 'Found `endif outside of macro conditional branch!' found !!!
Passed unmatched_endif_2.ys
<<EOT:3: ERROR: Local declaration in unnamed block is only supported in SystemVerilog mode!
Expected error pattern 'Local declaration in unnamed block is only supported in SystemVerilog mode!' found !!!
Passed unnamed_block.ys
Passed unnamed_genblk.ys
Passed unreachable_case_sign.ys
Passed upto.ys
Warning: wire '\wire_1' is assigned in a block at wire_and_var.sv:21.41-21.51.
Warning: reg '\reg_2' is assigned in a continuous assignment at wire_and_var.sv:22.57-22.66.
Warning: reg '\var_reg_2' is assigned in a continuous assignment at wire_and_var.sv:26.77-26.90.
Warning: wire '\wire_logic_1' is assigned in a block at wire_and_var.sv:30.65-30.81.
Warning: wire '\wire_integer_1' is assigned in a block at wire_and_var.sv:31.73-31.91.
Passed wire_and_var.ys
Passed dynamic_range_lhs.sh
gmake[2]: Leaving directory '/disk-samsung/freebsd-ports/cad/yosys/work/yosys-yosys-0.24/tests/verilog'

  Passed "make test".
nakengelhardt commented 1 year ago

These tests are testing the error handling, and check that the error is emitted as expected. Thus the "Expected error pattern ... found" messages for each error.