Open Henkru opened 1 year ago
I can only reproduce this issue when using read_verilog
with the -defer
option, which read
does by default. Using read_verilog
directly without that option works here and may be a suitable workaround for you.
The issue seems to be that deferred RTLIL generation for the top module doesn't trigger deferred RTLIL generation for the interface used by the top module which then results in the interface not being instantiated. The placeholder port for the modport is then being removed without actually adding the modport ports. This in turn ends up with an undeclared implicit 1-bit wire for bus.a
(the corresponding warning is present even without -defer
, a false positive, as the reference to bus.a
is later correctly resolved by hierarchy
, while with -defer
the warning is printed again after interfaces are supposed to be resolved).
I don't know how to fix this yet, as I'm not too familiar with the implementation of hierarchy
.
Thanks for the clarification. I can confirm that read_verilog -sv top.sv
works as a workaround.
Version
Yosys 0.24+10 (git sha1 69cbef966, clang 10.0.0-4ubuntu1 -fPIC -Os)
On which OS did this happen?
Linux
Reproduction Steps
When a SystemVerilog code contains an interface with wider fields than a single bit, it appears that the bus is being treated as a single bit wire rather than n bits. See the screenshot below.
top.sv
file.module top ( input clk, inf.Slave bus
);
endmodule
[options] mode cover
[engines] smtbmc
[script] read -sv -formal top.sv prep -top top
[files] top.sv
SBY 22:27:03 [top] base: top.sv:15: Warning: Identifier `\bus.a' is implicitly declared. SBY 22:27:03 [top] base: Warning: Wire top.\bus.a is used but has no driver. SBY 22:27:03 [top] base: finished (returncode=0) SBY 22:27:03 [top] prep: starting process "cd top/model; yosys -ql design_prep.log design_prep.ys" SBY 22:27:03 [top] prep: Warning: Wire top.\bus.a is used but has no driver.