Regarding removal of buffers and directly using the nets

[ratul619]

Feature Description

Hi ,

I have buffers in my netlist , any way not to use the buffers and use the input nets of the buffer directly downstream ?

If i put dont use on the buffers , i am getting Error that buffers are not there in the library.

sky130_fd_sc_hd__buf_1 _43_ (
    .A(_17_),
    .X(_13_)
  );
  sky130_fd_sc_hd__buf_1 _44_ (
    .A(_14_),
    .X(_10_)
  );
  sky130_fd_sc_hd__buf_1 _45_ (
    .A(_11_),
    .X(_07_)
  );

Thanks

[gatecat]

What Yosys script are you using?

[ratul619]

read design

read -sv rippler_adder.v hierarchy -top ripplemod proc; fsm; opt; memory; opt

synth -flatten;

    extract_fa -fa -v
    extract_fa -ha -v
    #set fa_map true

techmap -map /home/ratul619/IIT_study_VM/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/fa_map.v

dfflibmap -liberty ./sky130_fd_sc_hd__tt_025C_1v80.lib

mapping logic to mycells.lib

abc -liberty ./sky130_fd_sc_hd__tt_025C_1v80.lib

opt_clean -purge

write_verilog RA_synth.v

[Ravenslofty]

The recommended solution here would be to use techmap followed by opt_clean.

Given a Verilog file like this one called buffer_map.v:

module sky130_fd_sc_hd__buf_1(input A, output X)
\$_BUF_ _TECHMAP_REPLACE_ (.A(A), .Y(X));
endmodule

techmap -map buffer_map.v will replace the sky130 buffer cells with the Yosys-internal $_BUF_ cell, and then opt_clean will directly connect the input and output of the $_BUF_ cell, which achieves what you want.