Possible initialization issue in Xilinx DSP48E1 cell

[keszocze]

While working with the DSP48E1 I found the following code snippet: https://github.com/YosysHQ/yosys/blob/1cfedc90ce7b2bd63d75883a4e8c36fd44f0e4e7/techlibs/xilinx/cells_sim.v#L3612-L3619

I believe that line3167 should actually be

if (DREG == 1) initial Dr = 25'b0; 

i.e., check the DREG attribute instead of CREG to properly initialize the Dr register. But as I am totally new to Yosys I might be missing something. Is this the case? If so, I will gladly create a PR.

[nakengelhardt]

Indeed, that must be a typo!

[keszocze]

Indeed, that must be a typo!

I opened a corresponding PR

[nakengelhardt]

Thanks!