Open narutozxp opened 1 year ago
Note: memory_bram
is deprecated, we recommend using memory_libmap
instead.
Please post the full script; is uses the en signal when I try:
This is the result from the following script:
read_verilog top.v
proc
hierarchy -top sync_dual_port_ram_1
flatten
opt_expr
opt_clean
check
opt
wreduce
peepopt
opt_clean
share
opt_expr
opt_clean
memory -nomap
opt_clean
memory_bram -rules ./bram.txt
techmap -map ./bram_map.v
opt -fast -mux_undef -undriven -fine -nodffe -nosdff
memory_map
opt -undriven -fine -nodffe -nosdff
show
I think the reason why I got a suboptimal result is that I used the command “opt -nodffe -nosdff” instead of “opt”, but I don’t understand why this command would cause such an outcome.
Version
Yosys 0.28+4 (git sha1 7efc50367, clang 14.0.0-1ubuntu1 -fPIC -Os)
On which OS did this happen?
Linux
Reproduction Steps
The following is the content of my mapping rules file
The following is the file used by techmap pass
the bram synthesis flows are as follows:
the first module is synthesized into a group of ffs , however, the second one is synthesized into my aimed block ram with the constant 1 at the ren pin. It seems that the yosys can't make use of the "read_en" signal。
Expected Behavior
the first module should be synthesized into my aimed dpram with the ren controlled by read_en
Actual Behavior
the first module is synthesized into a group of ffs