Open YikeZhou opened 1 year ago
This needs a change in export_bvop
such that for shift cells with a signed A input, the A input is only sign extended up to the width of the Y output and then, if necessary due to smtlib restrictions on operand sizes, zero extended up to the width of B.
Version
Yosys 0.28+6 (git sha1 cee3cb31b, clang 10.0.0-4ubuntu1 -fPIC -Os)
On which OS did this happen?
Linux
Reproduction Steps
Verilog file:
Yosys script:
Expected Behavior
As far as I know,
4'sb1000
shouldn't be sign-extended to5'sb11000
in this situation. For example, whenoffset=2
,res
is expected to be2(4'b0010)
.First, according to this example from SystemVerilog standard (IEEE Std 1800-2017), the width of
4'sb1000 >> offset
is expected to be4
.Second, I tried this test case on ModelSim and Verilator. Both of them returned the value
2
.Actual Behavior
Output of Yosys:
Note the expression
(_ extract 3 0) (bvlshr #b11000 (|top#0| state))
in line 10. This indicates that whenoffset=2
, the output signalres
is6(4'b0110)
.So I thought this might be a bug.