"Failed to resolve identifier XXX for width detection" with System Verilog interface element

[janschiefer]

Version

Yosys 0.33+6 (git sha1 41b34a193, clang 16.0.0 -fPIC -Os)

On which OS did this happen?

Linux

Reproduction Steps

interface testinterface();

    logic [7:0] A;

    modport MP( input A );

endinterface

module test_yosys_bug(
    input logic clk,
    testinterface test_if
);

    bit test;
    initial test = 1'b0;

    always @( posedge clk )

        case(test_if.MP.A)
            8'b0: test <= !test;
            // ...
            default: test <= 1'b0;

        endcase

endmodule

module top(...);

testinterface t_if();

     test_yosys_bug test1(
            .test_if(t_if.MP)
        );

endmodule

Tis code works flawlessly with Verilator.

Expected Behavior

Detecting interface item item width without error.

Workaround, which actually defeats the usefulness of System Verilog interfaces:

interface testinterface();

    logic [7:0] A;

    modport MP( input A );

endinterface

module test_yosys_bug(
    input logic clk,
    testinterface test_if
);

    bit test;
    initial test = 1'b0;

    //Introduce additional local variable
    logic [7:0] A_tmp = test_if.MP.A;

    always @( posedge clk )

        case(A_tmp)
            8'b0: test <= !test;
            // ...
            default: test <= 1'b0;

        endcase

endmodule

module top(...);

(...)

testinterface t_if();

     test_yosys_bug test1(
             .clk(clk),
            .test_if(t_if.MP)
        );

(...)

endmodule

Actual Behavior

ERROR:

(...)

4.4.3. Executing AST frontend in derive mode using pre-parsed AST for module `\test_yosys_bug'.
Generating RTLIL representation for module `\test_yosys_bug'.
hdl/top.sv:24: ERROR: Failed to resolve identifier \test_if.MP.A for width detection!

[janschiefer]

Ok. This seems related to https://github.com/YosysHQ/yosys/issues/3592

But the solution proposed there doesn't fix the problem...