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Yosys Open SYnthesis Suite
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accept "inout" on interface modports #4159

Open ldoolitt opened 7 months ago

ldoolitt commented 7 months ago

Feature Description

As of yosys-0.37 at least, using "inout" in a modport yields

ERROR: syntax error, unexpected TOK_INOUT, expecting TOK_ID or TOK_INPUT or TOK_OUTPUT or ')'

Is this situation intentional or permanent?

ldoolitt commented 7 months ago

I'm not a SystemVerilog expert. I do know that inout modports are accepted by Vivado and Verilator. A few of them showed up in my $DAYJOB codebase. Hence this question.

nakengelhardt commented 7 months ago

Yosys only has very partial SystemVerilog support, the current read_verilog codebase is just not good enough to get anywhere near full support, although @zachjs has been doing his best to extend it. There are various plugins and converters for SystemVerilog input, such as sv2v or surelog. By the way, today's Yosys User Group meeting is also about this topic, the PULP folks will be presenting their tool svase.