Open ldoolitt opened 7 months ago
I'm not a SystemVerilog expert. I do know that inout modports are accepted by Vivado and Verilator. A few of them showed up in my $DAYJOB codebase. Hence this question.
Yosys only has very partial SystemVerilog support, the current read_verilog
codebase is just not good enough to get anywhere near full support, although @zachjs has been doing his best to extend it. There are various plugins and converters for SystemVerilog input, such as sv2v or surelog. By the way, today's Yosys User Group meeting is also about this topic, the PULP folks will be presenting their tool svase.
Feature Description
As of yosys-0.37 at least, using "inout" in a modport yields
Is this situation intentional or permanent?