verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections

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Yosys Open SYnthesis Suite

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Open zachjs opened 7 months ago

zachjs commented 7 months ago

AST_CONCAT and AST_TO_UNSIGNED are always unsigned, but may generate RTLIL that exclusively reference a signed wire.
AST_CONCAT may also contain a memory write.

Fixes #4158.