Closed povik closed 7 months ago
Not sure if this is an actual issue. I assume the target with the read
command that switches between the two Verilog frontends is consistent behavior on appropriately written scripts, and I don't know if it's defined what those are. In any case this behavior surprised me.
Isn't that what we fixed with #4130? Have you tried with latest master?
Isn't that what we fixed with https://github.com/YosysHQ/yosys/pull/4130?
Indeed looks like it. It doesn't reproduce on latest master.
Version
Yosys 0.37+74 (git sha1 c9f842f41, clang++ 11.1.0 -fPIC -Os)
On which OS did this happen?
macOS
Reproduction Steps
Expected Behavior
No matter if I am running Yosys with Verific or without, by the time the
stat
command is reached the module is fully elaborated and lowered to RTLIL.Actual Behavior
Without Verific, the module stays at
$abstract\top
even past thehierarchy
command. If I dohierarchy -top top
instead, then the module does get lowered.With Verific, Yosys has the expected behavior.