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Yosys Open SYnthesis Suite
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proc_rom: don't assert on big actionless switch. #4218

Closed kivikakk closed 7 months ago

kivikakk commented 7 months ago

See the test case. PROC_ROM will consider this for evaluation, even though -- without any actions -- lhs is empty (but still "uniform"). A zero-width memory is constructed, which later fails check with:

ERROR: Assert `width != 0' failed in kernel/mem.cc:518.

Ensure we don't proceed if there's nothing to encode.

Alternatively, do we want to reject this switch as meaningless? This came up in an Amaranth (188eb8d4) project; I've yet to investigate deeply why it's produced this, but either way Yosys probably doesn't want to give the assert it currently does here.

whitequark commented 7 months ago

Alternatively, do we want to reject this switch as meaningless?

RTLIL does allow switches with no cases, switches with no actions, etc.