In SystemVerilog, it is considered good style to indicate the source language used via the `begin_keywords directive. This is also good for upwards compatibility, to avoid source code breaking in the future, when identifiers used in the source might become keywords of future Verilog versions.
Often, SystemVerilog code intended for synthesis does not use any fancy new SystemVerilog features (and even uses the begin_keywords directive to indicate so). So the only thing preventing yosys from compiling some .v file is thebegin_keywords directive in it.
Feature Description
In SystemVerilog, it is considered good style to indicate the source language used via the `begin_keywords directive. This is also good for upwards compatibility, to avoid source code breaking in the future, when identifiers used in the source might become keywords of future Verilog versions.
Often, SystemVerilog code intended for synthesis does not use any fancy new SystemVerilog features (and even uses the
begin_keywords directive to indicate so). So the only thing preventing yosys from compiling some .v file is thebegin_keywords directive in it.