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Yosys Open SYnthesis Suite
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`share` stuck on a combinational loop #4260

Open povik opened 4 months ago

povik commented 4 months ago

Version

Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 11.1.0 -fPIC -Os)

On which OS did this happen?

macOS

Reproduction Steps

read_verilog <<EOF
module top(a, b, y);
    input wire a;
    input wire b;
    output wire y;

    wire j = k ? a : ~k;
    wire k = l ? ~j : b;
    wire l = j ? ~k : b;

    assign y = l;
endmodule
EOF
share

Expected Behavior

share not stuck

Actual Behavior

share stuck