Use of system functions in localparam value prevents resolution of port

[nakengelhardt]

Not 100% sure what the standard has to say about using a localparam defined inside a module in its port definitions, but given that these two examples work:

module works1 (
    output [N-1:0] foo
);
    localparam N = $clog2(4);

    assign foo = -1;
endmodule

module works2 (
    output [N:0] foo
);
    localparam N = 2;

    assign foo = -1;
endmodule

I think this should also work (and verific accept it too):

module fails (
    output [N:0] foo
);
    localparam N = $clog2(4);

    assign foo = -1;
endmodule

However with read_verilog the combination of using the parameter straight (not in an expression) and defining its value with a function call leads to an error:

-- Running command `read_verilog test.v' --

1. Executing Verilog-2005 frontend: test.v
Parsing Verilog input from `test.v' to AST representation.
Generating RTLIL representation for module `\fails'.
test.v:2: ERROR: Non-constant range in declaration of \foo

[jix]

It seems the SV standard is not particularly clear on whether this is allowed. I can't find any place that explicitly allows or forbids it, but given that in other instances (variables and type definitions) the standard explicitly requires the declaration to precede a reference, it would be reasonable to infer that the absence of such a requirement for parameters means that it is allowed.