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YosysHQ / yosys

Yosys Open SYnthesis Suite
https://yosyshq.net/yosys/
ISC License
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latch inferred in synthesis process #4276

Closed cemery123 closed 3 months ago

cemery123 commented 3 months ago

Version

Yosys 0.37+1 (git sha1 e1f4c5c9cbb, clang -fPIC -Os)

On which OS did this happen?

Linux

Reproduction Steps

read_verilog rtl.v; synth; write_verilog -noattr syn.v

Expected Behavior

synthesis successful and write_verilog syn.v

Actual Behavior

Abnormal crash in synthesis process and failed. I have attacthed the log file pending.zip

KrystalDelusion commented 3 months ago

I believe this is the same issue as #4160 and is fixed in the latest releases. Running the code locally with latest Yosys I do not get any error.