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Yosys Open SYnthesis Suite
https://yosyshq.net/yosys/
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Failed to Find a Submodule during Verilog Synthesis #4288

Closed yelen103 closed 3 months ago

yelen103 commented 3 months ago

Version

Yosys 0.37+1 (git sha1 e1f4c5c9cbb, clang -fPIC -Os)

On which OS did this happen?

Linux

Reproduction Steps

Hi, I am having problems with yosys synthesis. After yosys ran, I received the following error report: Module \DotProduct_block10' referenced in module\Subsystem' in cell `\u_cfblk36_inst' is not part of the design

Synthesis processes as follows: read_verilog Subsystem_org.v synth write_verilog Subsystem_yosys.v

The same design file 'Subsystem_org.v' can be successfully synthesized without error in the vivado synthesis tool, proving that a yosys problem appears to have occurred.

I uploaded all the source files in the attachment, as well as the incentive file 'Subsystem_tb.v'. We hope to help you to repeat the problem as soon as possible. Look forward to hearing from you yosys_3.zip

Expected Behavior

synthesis success

Actual Behavior

synthesis fail

KrystalDelusion commented 3 months ago

As the error says; \DotProduct_block10 is not in the Subsystem_org.v file. You need to read all of the source files before calling synth, not just the top module. You should also specify the top level module with synth -top Subsystem.

read_verilog *.v
synth -top Subsystem
write_verilog Subsystem_yosys.v

works without error.