Open DmitryZlobec opened 3 months ago
Minimised testcase:
module top(inout [11:0] GPIO, input _0_, input _1_, input _2_);
reg \GPIO_reg[1] ;
always @(posedge _0_, posedge _1_)
if (_1_) \GPIO_reg[1] <= 1'b1;
else \GPIO_reg[1] <= _2_;
assign GPIO[1] = \GPIO_reg[1] ;
endmodule
I think this might be a variant of #4168.
Version
Yosys 0.39+124 (git sha1 d73f71e81, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os)
On which OS did this happen?
Linux
Reproduction Steps
yosys top.sv tm1638_board.sv -p "synth_ecp5 -json top.json -top top" err.gz tm1638_board.sv.gz top.sv.gz
Expected Behavior
synthesis completes without using -noabc9
Actual Behavior
3.43.6. Executing SCC pass (detecting logic loops). Found 0 SCCs in module top. Found 0 SCCs. .... 3.43.19.3. Executing XAIGER backend. ERROR: Visited AIG node more than once; this could be a combinatorial loop that has not been broken