module top(
reg [1:0] clk;
reg signed [21:0] wire3;
reg [14:0] wire2;
reg [7:0] wire0;
wire [647:0] y;
operation_mod op_mod(
.clk({clk}),
.wire3({wire3}),
.wire2({wire2}),
.wire0({wire0}),
.y({y})
);
endmodule
module operation_mod(
input [1:0] clk,
input signed [21:0] wire3,
input [14:0] wire2,
input [7:0] wire0,
output [647:0] y
);
reg [11:0] reg10 = 0;
reg [19:0] reg9 = 0;
reg signed [19:0] reg8 = 0;
assign y = {reg10, reg9, reg8};
always @(posedge clk[0]) begin
if (wire0[0]) begin
reg8 <= wire3[19:0];
reg9 <= ~((1'b0) >= $signed(-((wire2[0]) ? 1'b0 : 1'b0)));
reg10 <= 0;
end else begin
reg8 <= $signed(reg8[19:0]);
reg9 <= wire3[19:0];
reg10 <= 0;
end
end
endmodule
Expected Behavior
Successfully finished Verilog frontend.
Actual Behavior
I encountered an assertion failure error while working with Yosys, specifically when processing a design that involves signed and unsigned signals. The error message provided is as follows:
It seems that this issue is specific to Yosys; the results from Vivado do not exhibit this behavior.
![Uploading image.png…]()
Ravenslofty
commented
3 months ago
Version
Yosys 0.39+149
On which OS did this happen?
Linux
Reproduction Steps
The text:
module top( reg [1:0] clk; reg signed [21:0] wire3; reg [14:0] wire2; reg [7:0] wire0; wire [647:0] y; operation_mod op_mod( .clk({clk}), .wire3({wire3}), .wire2({wire2}), .wire0({wire0}), .y({y}) ); endmodule module operation_mod( input [1:0] clk, input signed [21:0] wire3, input [14:0] wire2, input [7:0] wire0, output [647:0] y ); reg [11:0] reg10 = 0; reg [19:0] reg9 = 0; reg signed [19:0] reg8 = 0; assign y = {reg10, reg9, reg8}; always @(posedge clk[0]) begin if (wire0[0]) begin reg8 <= wire3[19:0]; reg9 <= ~((1'b0) >= $signed(-((wire2[0]) ? 1'b0 : 1'b0))); reg10 <= 0; end else begin reg8 <= $signed(reg8[19:0]); reg9 <= wire3[19:0]; reg10 <= 0; end end endmodule
Expected Behavior
Successfully finished Verilog frontend.
Actual Behavior
I encountered an assertion failure error while working with Yosys, specifically when processing a design that involves signed and unsigned signals. The error message provided is as follows:
It seems that this issue is specific to Yosys; the results from Vivado do not exhibit this behavior.
![Uploading image.png…]()