Processes without sync rules correspond to simple decision trees that directly correspond to always @* or always_comb blocks in Verilog, and do not need a warning.
This removes the need to suppress warnings during the RTLIL-to-Verilog conversion performed by Amaranth.
Processes without sync rules correspond to simple decision trees that directly correspond to
always @*oralways_combblocks in Verilog, and do not need a warning.This removes the need to suppress warnings during the RTLIL-to-Verilog conversion performed by Amaranth.