In common with most EDA tools, Verific produces warnings on a lot of benign, commonly used (System-)Verilog coding styles. This is not in line with the Yosys philosophy, where warnings usually indicate a significant problem in the design that is likely to result in missynthesis.
The following messages should have their default severity decreased from WARNING to INFO:
VERIFIC-WARNING [VERI-1209] foo.sv:98: expression size 7 truncated to fit in target size 6
VERIFIC-WARNING [VERI-1142] foo.sv:55: system task 'display' is ignored for synthesis
VERIFIC-WARNING [VERI-2418] foo.svh:503: parameter 'all_cfgs_gp' declared inside package 'bp_common_pkg' shall be treated as localparam
(please suggest further nominations as you encounter them)
As a motivating data point, using verific -set-info on the first three reduced the warning load from 176 mostly useless warnings to 10 very relevant warnings on the BlackParrot core.
In common with most EDA tools, Verific produces warnings on a lot of benign, commonly used (System-)Verilog coding styles. This is not in line with the Yosys philosophy, where warnings usually indicate a significant problem in the design that is likely to result in missynthesis.
The following messages should have their default severity decreased from
WARNINGtoINFO:VERIFIC-WARNING [VERI-1209] foo.sv:98: expression size 7 truncated to fit in target size 6VERIFIC-WARNING [VERI-1142] foo.sv:55: system task 'display' is ignored for synthesisVERIFIC-WARNING [VERI-2418] foo.svh:503: parameter 'all_cfgs_gp' declared inside package 'bp_common_pkg' shall be treated as localparamAs a motivating data point, using
verific -set-infoon the first three reduced the warning load from 176 mostly useless warnings to 10 very relevant warnings on the BlackParrot core.