drivertools: Utility code for indexing and traversing signal drivers

[jix]

This is a work in progress version of a new yosys kernel utility to simplify netlist traversal. The motivating use case is the upcoming functional backend but it also should also simplify some common operations/queries that come up repeatedly in various passes.

It adds DriveBit, DriveChunk and DriveSpec types which are similar to SigBit, SigChunk and SigSpec but can also directly represent cell ports, undriven bits and multiple drivers. For indexing an RTLIL module and for querying signal drivers it comes with a DriverMap type which is somewhat similar to a SigMap but is guaranteed to produce signal drivers as returned representatives.

A DriverMap can also optionally preserve connections via intermediate wires (e.g. querying the driver of a cell input port will return a connected intermediate wire, querying the driver of that wire will return the cell output port that's driving the wire). Currently the behavior is hard-coded to preserve wires with the keep attribute, but this should be configurable.

As a temporary example this includes an example_dt pass which recursively traverses a netlist and performs a topological sort of the cells and signals, logging everything.

[jix]

I did some minor cleanup of the commit history and moved the temporary example pass as well as parts of the functional backend that go beyond drivertools into a separate branch at https://github.com/jix/yosys/tree/functional.