Closed mmicko closed 2 months ago
Each module is represented by Netlist object in Verific. It's owner is Cell and it's owner is Library object, that matches "work" specified when reading Verilog or VHDL sources.
There is always such object so no need for NULL checks.
Each module is represented by Netlist object in Verific. It's owner is Cell and it's owner is Library object, that matches "work" specified when reading Verilog or VHDL sources.
There is always such object so no need for NULL checks.