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Yosys Open SYnthesis Suite
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Add support for SystemVerilog's `==?` and `!=?` operators #4374

Open jmi2k opened 1 month ago

jmi2k commented 1 month ago

Feature Description

The ==? and !=? operators seem to be defined since IEEE 1800-2005 and allow x and z bits on the RHS to be ignored while performing (in)equality comparison. This greatly simplifies writing down comparisons where only a few bits scattered through a given value are relevant, currently requiring a long LHS expression to compact them.