CXXRTL: Information loss when outputs are aliased

[noeamiot]

Version

Yosys 0.39

On which OS did this happen?

Linux

Reproduction Steps

For the following and_ti.v file:

module top(input a0, input a1, input b0, input b1, input z, output c0, output c1);
    wire a0b0, a0b1, a1b0, a1b1;
    wire a0b1z, a1b0z;
    wire culprit;

    assign a0b0 = a0 & b0;
    assign a0b1 = a0 & b1;
    assign a1b0 = a1 & b0;
    assign a1b1 = a1 & b1;

    //assign a1b0 = a1b0 ^ z;
    //assign a0b1 = a0b1 ^ z;
    assign a0b1z = a0b1 ^ z;
    assign a1b0z = a1b0 ^ z;

    //assign c0 = a0b0 ^ (a0b1 ^ z);
    //assign c1 = a1b1 ^ (a1b0 ^ z);
    assign culprit = a1b1 ^ a1b0z; 
    assign c0 = culprit;
    assign c1 = a0b0 ^ a0b1z;
endmodule

The workflow used is simple:

read_verilog and_ti.v 
write_cxxrtl -O6 -g4 -header cxxrtl_and_ti.cpp

Gives the following debug information for the wires c0 and c1 :

items->add(path + "culprit", debug_item(debug_eval_outline, p_culprit, 0), metadata_map({
    { "src", "and_ti.v:4.10-4.17" },
}));
...
items->add(path + "c1", debug_item(p_c1, 0, debug_item::OUTPUT|debug_item::DRIVEN_COMB), metadata_map({
    { "src", "and_ti.v:1.79-1.81" },
}));
items->add(path + "c0", debug_item(debug_eval_outline, p_culprit, 0), metadata_map({
    { "src", "and_ti.v:4.10-4.17" },
}));

There are other combinations of HDL or -O flags that can lead to this behavior, sometimes on an outline like here, sometimes on normal wires.

Expected Behavior

There exists a way to retrieve the information that c0 is an output wire like for c1.

Actual Behavior

There is no way to know that c0 is an output because it is aliased to another wire that is not an output.

[whitequark]

Thanks for the report. Yeah, ports should probably just not be aliasable.

[whitequark]

Do you think you could write a patch?

[noeamiot]

Sure !

[noeamiot]

Resolved by #4406.