RCA:
Like the code blow, iteration variable forvar14 is signed. However, the iteration variable lost the signed information during the ast simplify. For example, the value of forvar14 should be $signed(3'h0) instead of 3'h0 in the first loop cycle.
reg signed [2:0] forvar14 = (1'h0);
for (forvar14 = (1'h0); (forvar14 < (1'h1)); forvar14 = (forvar14 + (1'h1))) begin
.......
end
Fixes:
backends/verilog/verilog_backend.cc
Signed should be writed while dump verilog;
frontends/ast/genrtlil.cc
Before this change, children[0] will use the children[1]'s width_hint and sign_hint when genRTLIL, because they use the same variables and children[1]'s will overide children[0]'s.
frontends/ast/simplify.cc
Record iteration variable is signed or not;
Test
A case was provided in #4402 , use PR branch to build a new yosys, read the 'rtl.v' and dump the verilog after synthesis. Then follow the reproduce steps in issue #4402 , result will meet expectations.
Reseaon issue #4402
RCA: Like the code blow, iteration variable
forvar14is signed. However, the iteration variable lost the signed information during the ast simplify. For example, the value offorvar14should be$signed(3'h0)instead of3'h0in the first loop cycle.Fixes:
backends/verilog/verilog_backend.cc Signed should be writed while dump verilog;
frontends/ast/genrtlil.cc Before this change, children[0] will use the children[1]'s
width_hintandsign_hintwhengenRTLIL, because they use the same variables and children[1]'s will overide children[0]'s.frontends/ast/simplify.cc Record iteration variable is signed or not;
Test A case was provided in #4402 , use PR branch to build a new yosys, read the 'rtl.v' and dump the verilog after synthesis. Then follow the reproduce steps in issue #4402 , result will meet expectations.