Yosys Verilog Parsing Error: Unable to Synthesize After Reading File

[LoSyTe]

Version

yosys 0.41+126

On which OS did this happen?

Linux

Reproduction Steps

Hello, I encountered an error while using Yosys to read a Verilog file. The steps and the error message are as follows:

After this error, the parsing process is interrupted. I have checked the Verilog file for syntax errors but couldn't find any obvious issues. I am using the latest version of Yosys.

Attached is the Verilog file (design.v) that triggers the error. Thank you in advance for your attention to this matter. I look forward to hearing from you regarding this issue. design_file.zip

Expected Behavior

synthesis success

Actual Behavior

synthesis fail

[KrystalDelusion]

Changing lines 31 and 32 to the following makes it compile fine:

                  reg289[(3'h6):(3'h5)] : {"Q",
                      ($unsigned((8'hb6)) ? "t" : "e")}));

Looking at the source where the assert is being raised it seems to be a problem with the parsing of string constants: // create an AST node for a constant (using a string in bit vector form as value). The git blame in that section also has the commit message "Fixed constant "cond ? string1 : string2" with strings of different size," which leads me to suspect that this is the same bug that was previously believed to be fixed. Extending the "t" string to the same length as "eLOYX7WZioxFD2iW" also fixes the problem, so that does seem to be what is happening, however swapping the order of strings such that the longer string is first also fixes the problem.

[KrystalDelusion]

Minimal example (for the error):

module top ();
wire [15:0] x = {"1", "\0"};
endmodule

wire [23:0] y = {"1", 1 ? "a" : "bc"}; is closer to the example given here, combining both the problem above and the zero extension used in the ternary.