This makes two changes to allow reading in IO liberty files, for e.g. verification or simulation purposes where the Verilog simulation models are too non-synthesisable for Yosys to be able to handle them:
support for the three_state attribute which specifies a condition on which an output is tristated, converted into a $tribuf
inouts with a missing function aren't skipped, as the library we are using uses them for power pins
This makes two changes to allow reading in IO liberty files, for e.g. verification or simulation purposes where the Verilog simulation models are too non-synthesisable for Yosys to be able to handle them:
three_stateattribute which specifies a condition on which an output is tristated, converted into a$tribufinouts with a missing function aren't skipped, as the library we are using uses them for power pins