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Yosys Open SYnthesis Suite
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IDES4_MEM gowin module is missing #4453

Open LaneaLucy opened 3 months ago

LaneaLucy commented 3 months ago

Version

Yosys 0.42+12 (git sha1 62bff3a20, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os)

On which OS did this happen?

Linux

Reproduction Steps

try to synthesize the output of litex

to get the verilog file (im running the command in "/home/lanealucy/litex/"): python3 -m litex_boards.targets.sipeed_tang_primer_20k --build

here a example yosys script

verilog_defaults -push
verilog_defaults -add -defer
read_verilog /home/lanealucy/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v
read_verilog /home/lanealucy/litex/build/sipeed_tang_primer_20k/gateware/sipeed_tang_primer_20k.v
verilog_defaults -pop
attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0

synth_gowin  -top sipeed_tang_primer_20k
write_json  sipeed_tang_primer_20k.json

Expected Behavior

synthesize

Actual Behavior

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.42+12 (git sha1 62bff3a20, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os)

-- Executing script file `sipeed_tang_primer_20k.ys' --

1. Executing Verilog-2005 frontend: /home/lanealucy/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v
Parsing Verilog input from `/home/lanealucy/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v' to AST representation.
Storing AST representation for module `$abstract\VexRiscv'.
Storing AST representation for module `$abstract\DataCache'.
Storing AST representation for module `$abstract\InstructionCache'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /home/lanealucy/litex/build/sipeed_tang_primer_20k/gateware/sipeed_tang_primer_20k.v
Parsing Verilog input from `/home/lanealucy/litex/build/sipeed_tang_primer_20k/gateware/sipeed_tang_primer_20k.v' to AST representation.
Storing AST representation for module `$abstract\sipeed_tang_primer_20k'.
Successfully finished Verilog frontend.

3. Executing ATTRMAP pass (move or copy attributes).

4. Executing SYNTH_GOWIN pass.

4.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/gowin/cells_sim.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/gowin/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT1'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\LUT3'.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\__APICULA_LUT5'.
Generating RTLIL representation for module `\__APICULA_LUT6'.
Generating RTLIL representation for module `\__APICULA_LUT7'.
Generating RTLIL representation for module `\__APICULA_LUT8'.
Generating RTLIL representation for module `\MUX2'.
Generating RTLIL representation for module `\MUX2_LUT5'.
Generating RTLIL representation for module `\MUX2_LUT6'.
Generating RTLIL representation for module `\MUX2_LUT7'.
Generating RTLIL representation for module `\MUX2_LUT8'.
Generating RTLIL representation for module `\DFF'.
Generating RTLIL representation for module `\DFFE'.
Generating RTLIL representation for module `\DFFS'.
Generating RTLIL representation for module `\DFFSE'.
Generating RTLIL representation for module `\DFFR'.
Generating RTLIL representation for module `\DFFRE'.
Generating RTLIL representation for module `\DFFP'.
Generating RTLIL representation for module `\DFFPE'.
Generating RTLIL representation for module `\DFFC'.
Generating RTLIL representation for module `\DFFCE'.
Generating RTLIL representation for module `\DFFN'.
Generating RTLIL representation for module `\DFFNE'.
Generating RTLIL representation for module `\DFFNS'.
Generating RTLIL representation for module `\DFFNSE'.
Generating RTLIL representation for module `\DFFNR'.
Generating RTLIL representation for module `\DFFNRE'.
Generating RTLIL representation for module `\DFFNP'.
Generating RTLIL representation for module `\DFFNPE'.
Generating RTLIL representation for module `\DFFNC'.
Generating RTLIL representation for module `\DFFNCE'.
Generating RTLIL representation for module `\VCC'.
Generating RTLIL representation for module `\GND'.
Generating RTLIL representation for module `\IBUF'.
Generating RTLIL representation for module `\OBUF'.
Generating RTLIL representation for module `\TBUF'.
Generating RTLIL representation for module `\IOBUF'.
Generating RTLIL representation for module `\ELVDS_OBUF'.
Generating RTLIL representation for module `\TLVDS_OBUF'.
Generating RTLIL representation for module `\OSER4'.
Generating RTLIL representation for module `\OSER8'.
Generating RTLIL representation for module `\OSER10'.
Generating RTLIL representation for module `\OVIDEO'.
Generating RTLIL representation for module `\OSER16'.
Generating RTLIL representation for module `\IDES4'.
Generating RTLIL representation for module `\IDES8'.
Generating RTLIL representation for module `\IDES10'.
Generating RTLIL representation for module `\IVIDEO'.
Generating RTLIL representation for module `\IDES16'.
Generating RTLIL representation for module `\IDDR'.
Generating RTLIL representation for module `\IDDRC'.
Generating RTLIL representation for module `\ODDR'.
Generating RTLIL representation for module `\ODDRC'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\ALU'.
Generating RTLIL representation for module `\RAM16S1'.
Generating RTLIL representation for module `\RAM16S2'.
Generating RTLIL representation for module `\RAM16S4'.
Generating RTLIL representation for module `\RAM16SDP1'.
Generating RTLIL representation for module `\RAM16SDP2'.
Generating RTLIL representation for module `\RAM16SDP4'.
Generating RTLIL representation for module `\SP'.
Generating RTLIL representation for module `\SPX9'.
Generating RTLIL representation for module `\SDP'.
Generating RTLIL representation for module `\SDPX9'.
Generating RTLIL representation for module `\DP'.
Generating RTLIL representation for module `\DPX9'.
Generating RTLIL representation for module `\rPLL'.
Generating RTLIL representation for module `\PLLVR'.
Generating RTLIL representation for module `\OSC'.
Generating RTLIL representation for module `\OSCZ'.
Generating RTLIL representation for module `\OSCF'.
Generating RTLIL representation for module `\OSCH'.
Generating RTLIL representation for module `\OSCW'.
Generating RTLIL representation for module `\OSCO'.
Successfully finished Verilog frontend.

4.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/gowin/cells_xtra.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/gowin/cells_xtra.v' to AST representation.
Generating RTLIL representation for module `\MUX2_MUX8'.
Generating RTLIL representation for module `\MUX2_MUX16'.
Generating RTLIL representation for module `\MUX2_MUX32'.
Generating RTLIL representation for module `\MUX4'.
Generating RTLIL representation for module `\MUX8'.
Generating RTLIL representation for module `\MUX16'.
Generating RTLIL representation for module `\MUX32'.
Generating RTLIL representation for module `\LUT5'.
Generating RTLIL representation for module `\LUT6'.
Generating RTLIL representation for module `\LUT7'.
Generating RTLIL representation for module `\LUT8'.
Generating RTLIL representation for module `\DL'.
Generating RTLIL representation for module `\DLE'.
Generating RTLIL representation for module `\DLC'.
Generating RTLIL representation for module `\DLCE'.
Generating RTLIL representation for module `\DLP'.
Generating RTLIL representation for module `\DLPE'.
Generating RTLIL representation for module `\DLN'.
Generating RTLIL representation for module `\DLNE'.
Generating RTLIL representation for module `\DLNC'.
Generating RTLIL representation for module `\DLNCE'.
Generating RTLIL representation for module `\DLNP'.
Generating RTLIL representation for module `\DLNPE'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\IODELAY'.
Generating RTLIL representation for module `\IEM'.
Generating RTLIL representation for module `\ROM16'.
Generating RTLIL representation for module `\ROM'.
Generating RTLIL representation for module `\ROMX9'.
Generating RTLIL representation for module `\rSDP'.
Generating RTLIL representation for module `\rSDPX9'.
Generating RTLIL representation for module `\rROM'.
Generating RTLIL representation for module `\rROMX9'.
Generating RTLIL representation for module `\pROM'.
Generating RTLIL representation for module `\pROMX9'.
Generating RTLIL representation for module `\SDPB'.
Generating RTLIL representation for module `\SDPX9B'.
Generating RTLIL representation for module `\DPB'.
Generating RTLIL representation for module `\DPX9B'.
Generating RTLIL representation for module `\PADD18'.
Generating RTLIL representation for module `\PADD9'.
Generating RTLIL representation for module `\MULT9X9'.
Generating RTLIL representation for module `\MULT18X18'.
Generating RTLIL representation for module `\MULT36X36'.
Generating RTLIL representation for module `\MULTALU36X18'.
Generating RTLIL representation for module `\MULTADDALU18X18'.
Generating RTLIL representation for module `\MULTALU18X18'.
Generating RTLIL representation for module `\ALU54D'.
Generating RTLIL representation for module `\BUFG'.
Generating RTLIL representation for module `\BUFS'.
Generating RTLIL representation for module `\PLL'.
Generating RTLIL representation for module `\TLVDS_IBUF'.
Generating RTLIL representation for module `\TLVDS_TBUF'.
Generating RTLIL representation for module `\TLVDS_IOBUF'.
Generating RTLIL representation for module `\ELVDS_IBUF'.
Generating RTLIL representation for module `\ELVDS_TBUF'.
Generating RTLIL representation for module `\ELVDS_IOBUF'.
Generating RTLIL representation for module `\MIPI_IBUF'.
Generating RTLIL representation for module `\MIPI_IBUF_HS'.
Generating RTLIL representation for module `\MIPI_IBUF_LP'.
Generating RTLIL representation for module `\MIPI_OBUF'.
Generating RTLIL representation for module `\MIPI_OBUF_A'.
Generating RTLIL representation for module `\I3C_IOBUF'.
Generating RTLIL representation for module `\CLKDIV'.
Generating RTLIL representation for module `\DHCEN'.
Generating RTLIL representation for module `\DLL'.
Generating RTLIL representation for module `\DLLDLY'.
Generating RTLIL representation for module `\FLASH96K'.
Generating RTLIL representation for module `\FLASH256K'.
Generating RTLIL representation for module `\FLASH608K'.
Generating RTLIL representation for module `\DCS'.
Generating RTLIL representation for module `\DQCE'.
Generating RTLIL representation for module `\FLASH128K'.
Generating RTLIL representation for module `\MCU'.
Generating RTLIL representation for module `\USB20_PHY'.
Generating RTLIL representation for module `\ADC'.
Generating RTLIL representation for module `\BANDGAP'.
Generating RTLIL representation for module `\CLKDIV2'.
Generating RTLIL representation for module `\DCC'.
Generating RTLIL representation for module `\DHCENC'.
Generating RTLIL representation for module `\EMCU'.
Generating RTLIL representation for module `\FLASH64K'.
Generating RTLIL representation for module `\FLASH64KZ'.
Generating RTLIL representation for module `\I3C'.
Generating RTLIL representation for module `\IODELAYA'.
Generating RTLIL representation for module `\IODELAYC'.
Generating RTLIL representation for module `\SPMI'.
Generating RTLIL representation for module `\IODELAYB'.
Generating RTLIL representation for module `\PLLO'.
Generating RTLIL representation for module `\DCCG'.
Generating RTLIL representation for module `\FLASH96KA'.
Generating RTLIL representation for module `\MIPI_DPHY_RX'.
Generating RTLIL representation for module `\CLKDIVG'.
Successfully finished Verilog frontend.

4.3. Executing HIERARCHY pass (managing design hierarchy).

4.4. Executing AST frontend in derive mode using pre-parsed AST for module `\sipeed_tang_primer_20k'.
Generating RTLIL representation for module `\sipeed_tang_primer_20k'.

4.4.1. Analyzing design hierarchy..
Top module:  \sipeed_tang_primer_20k

4.4.2. Executing AST frontend in derive mode using pre-parsed AST for module `\VexRiscv'.
Generating RTLIL representation for module `\VexRiscv'.
ERROR: Module `\IDES4_MEM' referenced in module `\sipeed_tang_primer_20k' in cell `\IDES4_MEM_15' is not part of the design.
whitequark commented 3 months ago

to get the verilog file (im running the command in "/home/lanealucy/litex/"):

Please attach the complete reproduction steps to this issue, including all files required to reproduce it without depending on third-party software. In this case this would be all of the Verilog files your script references.

LaneaLucy commented 3 months ago

sipeed_tang_primer_20k.zip

leviathanch commented 1 month ago

Hi, I've got the exact same problem!

leviathanch commented 1 month ago

There's a IDES4_MEM in /opt/gowin-1.9.8/IDE/bin/prim_syn.v but no IDES4_MEM_15 It might be an issue with Apypula respectively with Litex itself

leviathanch commented 1 month ago

OK, it's IDES4_MEM which is missing, I've just checked in the Verilog code

//------------------------------------------------------------------------------ // Instance IDES4_MEM_15 of IDES4_MEM Module. //------------------------------------------------------------------------------ IDES4_MEM IDES4_MEM_15( // Inputs. .CALIB (1'd0), .D (gw2ddrphy_dq_i15), .FCLK (sys2x_clk), .ICLK (gw2ddrphy_dqsr901), .PCLK (sys_clk), .RADDR (gw2ddrphy_rdpntr1), .RESET (sys_rst), .WADDR (gw2ddrphy_wrpntr1),

// Outputs.
.Q0    (gw2ddrphy_bitslip15_i[0]),
.Q1    (gw2ddrphy_bitslip15_i[1]),
.Q2    (gw2ddrphy_bitslip15_i[2]),
.Q3    (gw2ddrphy_bitslip15_i[3])

);

The issue is with Apycula not providing this cell as a dependency

leviathanch commented 1 month ago

OK, no, seems to be a problem in Yosys after all

leviathanch commented 1 month ago

I made a pull request solving this issue https://github.com/YosysHQ/yosys/pull/4545