support error for Aggregate Initialization and Replication

[yelen103]

Version

Yosys 0.37+1 (git sha1 e1f4c5c9cbb, clang -fPIC -Os)

On which OS did this happen?

Linux

Reproduction Steps

hlblk167_reg <= '{2{8'b00000000}}; This line of code is designed to initialize each element of the hlblk167_reg array to 8'b000000000. That is, the initialization of curly braces ('{...}) and the copy symbol ('{n{value}}), but this does not seem to be possible in yosys and the error is unexpected OP_CAST Our syntax should be error-free, but the synthesis is wrong.

yosys.zip

Subsystem.sv is set as the top-level file

Expected Behavior

There are no synthesis errors

Actual Behavior

appeared Synthesis errors

[georgerennie]

Yosys support for SystemVerilog is limited and it seems doesn't include those casts. That style of cast isn't in Verilog-2005, from what I can tell it appeared in 8.13 Assignment Patterns of IEEE 1800-2005, the 2005 SV standard.

I'm not very familiar with HDL coder, but maybe you can set it to export Verilog-2005 instead of SystemVerilog? If not consider using sv2v to preprocess your files or the commercial tabbycad suite from YosysHQ, both of which should support this.