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Yosys Open SYnthesis Suite
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Nanoxplore synthesis does not works when using abc9 flow #4606

Open samhanic opened 2 months ago

samhanic commented 2 months ago

Version

Yosys 0.45 (git sha1 9ed031ddd588442f22be13ce608547a5809b62f0, g++ 13.3.0 -fPIC -O3)

On which OS did this happen?

Linux

Reproduction Steps

Create any design.v file containing combinational logic. Run command: yosys -p "read_verilog design.v; synth_nanoxplore -abc9 ; write_json design.json"

Expected Behavior

Design synthetises and outputs the design netlist in design.json file.

Actual Behavior

Yosys errors out at ABC9 step:

2.46.11. Executing ABC9_OPS pass (helper functions for ABC9).
ERROR: Module 'NX_LUT' with (* abc9_lut *) has no specify entries.
mmicko commented 1 month ago

Hi. Sorry for the late response. This would still need exact timings we need to get from the vendor to work properly. Initially we played with some estimated data, but it would be better to rely on real data instead. So this issue is currently on hold.