search

YosysHQ / yosys

Yosys Open SYnthesis Suite
https://yosyshq.net/yosys/
ISC License
3.51k stars 895 forks source link

Fix: handle VCD variable references with and without whitespace #4620

Closed RCoeurjoly closed 2 weeks ago

RCoeurjoly commented 1 month ago

What are the reasons/motivation for this change?

Fixes https://github.com/YosysHQ/yosys/issues/4617.

Explain how this is achieved.

We detect if a variable reference in the VCD file contains a space between the signal name and the bit range. If no space is detected, the bit or part-select is parsed and removed from the signal name.

If applicable, please suggest to reviewers how they can test the change.

In addition to the added test case, I processed the neorv32 design with its GHDL-generated VCD file, and the sim pass did not report any issues. It might be helpful to test with other real-world examples, but I believe the current testing is sufficient to verify the fix

RCoeurjoly commented 1 month ago

Just needed to be rebased on vcd2fst integration when that one is merged. addr variable could use a better name as well.

Would wait till after the release before merging this, so we can try out more designs and check for regressions

Rebased on main. Changed addr for index_or_range.