Set VHDL assert condition initial state if fed by FF

[mmicko]

What are the reasons/motivation for this change? If we have assert that is inside VHLD process, it fails since condition signal is coming from uninitialized FF. Please note that this primitive is VHDL only so it will not affect SVA code path. Also there is left-over from past and there was never an "assume" attribute to convert this to assume.

    assert (conv_integer(addr) >= sram'low and conv_integer(addr) <= sram'high) report "out of bounds for read" severity error;
    rdata <= sram(conv_integer(addr));
    process(clk)
    begin
        if clk'event and clk = '1' then
            if wen = '1' then
                assert (conv_integer(addr) >= sram'low and conv_integer(addr) <= sram'high) report "out of bounds for write" severity error;
                sram(conv_integer(addr)) <= wdata;
            end if;
        end if;
    end process;

Explain how this is achieved. Initial state in condition wire is set to 1, making assert not trigger on its undefined state. Since condition signal may originate from any internal signal (including register) we are checking if it is public. Note that it will use register condition directly only if outside process block.