Add simulation model for Xilinx BRAM

[sifferman]

Feature Description

Hello.

My RTL's post-synthesis simulation was failing regression, and I tracked it down to an issue with the BRAM. I just realized that the Xilinx RAMB modules in techlibs/xilinx/cells_sim.v are not implemented for simulation.

Ideally, techlibs/xilinx/cells_sim.v should implement a simulation model for all BRAMs, which can basically be copied from Xilinx's Unisim Library (under Apache 2.0).

• https://github.com/Xilinx/XilinxUnisimLibrary/blob/master/verilog/src/unisims/RAMB18E1.v
• https://github.com/Xilinx/XilinxUnisimLibrary/blob/master/verilog/src/unisims/RAMB18E2.v
• https://github.com/Xilinx/XilinxUnisimLibrary/blob/master/verilog/src/unisims/RAMB36E1.v
• https://github.com/Xilinx/XilinxUnisimLibrary/blob/master/verilog/src/unisims/RAMB36E2.v

However, Xilinx's models can't be used directly because they are incompatible with Icarus and Verilator.

Any thoughts on this? I would be happy to do a pull if it would be helpful.