Module parameters are not affected by setundef pass

[kamilrakoczy]

Version

Yosys 0.47+22 (git sha1 cef87cc17, g++ 12.2.0-14 -fPIC -O3)

On which OS did this happen?

Linux

Reproduction Steps

Process SystemVerilog code (a.sv):

module foo #(parameter [1:0] a) (output [1:0] o);
    assign o = a;
endmodule

module top(output [1:0] o);
    foo #(2'b0x) foo(o);
endmodule

with following commands:

read_verilog -sv a.sv
setundef -zero -params
write_json out.json

Expected Behavior

File out.json should contain entry: "parameters": { "$1": "00" } responsible for foo's a parameter.

Actual Behavior

File out.json contains entry: "parameters": { "$1": "0x" } responsible for foo's a parameter.