Inconsistent simulation before and after yosys synthesis

[iagrigorov]

Version

Yosys 0.44 (git sha1 80ba43d26, g++ 11.4.0-2ubuntu1~20.04 -fPIC -O3)

On which OS did this happen?

Linux

Reproduction Steps

1. Install the necessary dependencies (skip this step if you have already installed verilator and zip):

   sudo apt-get install zip verilator

2. Download the attached .zip archive. Then change to the directory where this archive is located and unpack it:

   unzip files.zip

3. Go to files directory:

   cd files

4. Launch yosys like this:

   yosys -p"read_verilog test_07_14_00_1.v; proc; opt -nodffe; memory; pmuxtree; flatten -scopename; opt -nodffe -fast; aigmap; write_verilog test_07_14_00_1_dut.v"

5. Change the top module name of the synthesized module:

   sed -i 's/module test/module test_dut/g' test_07_14_00_1_dut.v

6. Launch verilator like this:

   verilator test_07_14_00_1.v test_07_14_00_1_dut.v test_07_14_00_1_testbench.sv -Wno-fatal +1364-2005ext+v +1800-2017ext+sv --binary --top-module test_testbench

7. Launch the simulation:

   ./obj_dir/Vtest_testbench

   files.zip

Expected Behavior

The expected behavior is the successful simulation result (without any discrepancies between the source model and the synthesized model).

Actual Behavior

verilator gives the following output:

 \in1_gold = 1
 \in2_gold = 1
 \in_gold = 1
 \ctrl_gold = 1
DUT Error at time                   30
 \out :
Expected value 0, Got Value 1
[3500] %Fatal: test_07_14_00_1_testbench.sv:78: Assertion failed in TOP.test_testbench
%Error: test_07_14_00_1_testbench.sv:78: Verilog $stop
Aborting...
Aborted (core dumped)

[jix]

Synthesis does not preserve timing annotations but your comparison setup expects it to. Additionally it seems like your input is part of a general verilog test suite. Yosys supports only synthesizable verilog and as such running it on a general test suite is expected to fail in various ways.