Inconsistent simulation before and after yosys synthesis(2)

[iagrigorov]

Version

Yosys 0.44 (git sha1 80ba43d26, g++ 11.4.0-2ubuntu1~20.04 -fPIC -O3)

On which OS did this happen?

Linux

Reproduction Steps

1. Install the necessary dependencies (skip this step if you have already installed verilator and zip):

   sudo apt-get install zip verilator

2. Download the attached .zip archive. Then change to the directory where this archive is located and unpack it:

   unzip files.zip

3. Go to files directory:

   cd files

4. Launch yosys like this:

   yosys -p"read_verilog spi_clgen.v spi_shift.v spi_top.v; proc; opt -nodffe; memory; pmuxtree; flatten -scopename; opt -nodffe -fast; aigmap; write_verilog spi_top_dut.v"

5. Change the top module name of the synthesized module:

   sed -i 's/module spi_top/module spi_top_dut/g' spi_top_dut.v

6. Launch verilator like this:

   verilator spi_clgen.v spi_shift.v spi_top.v spi_top_dut.v spi_top_testbench.sv -Wno-fatal +1364-2005ext+v +1800-2017ext+sv --binary --top-module spi_top_testbench

7. Launch the simulation:

   ./obj_dir/Vspi_top_testbench

   files.zip

Expected Behavior

The expected behavior is the successful simulation result (without any discrepancies between the source model and the synthesized model).

Actual Behavior

verilator gives the following output:

 \wb_clk_i_gold = 1
 \wb_rst_i_gold = 0
 \wb_adr_i_gold = 29
 \wb_dat_i_gold =  654853043
 \wb_sel_i_gold = 13
 \wb_we_i_gold = 1
 \wb_stb_i_gold = 0
 \wb_cyc_i_gold = 1
 \miso_pad_i_gold = 1
DUT Error at time                  140
 \wb_dat_o :
Expected value          0, Got Value 2189422950
[14500] %Fatal: spi_top_testbench.sv:144: Assertion failed in TOP.spi_top_testbench
%Error: spi_top_testbench.sv:144: Verilog $stop
Aborting...
Aborted (core dumped)

[jix]

Again, among other issues, the design contains timing annotations that will be simulated by verilator but ignored during synthesis, thus a duplicate of #4743.

I already explained in #4743 that this is expected to fail. You are clearly running auto-generated testbenches on arbitrary verilog code you found on the internet and then file issues for any failures without making any serious attempt at figuring out whether a failure is to be expected due to the nature of verilog synthesis. As this is a waste of everyone's time, please stop filing such issues.