povik
commented
2 hours ago Small reproducer:
read_slang <<EOF
module top;
reg x, b;
reg [2:0] a;
reg [2:0] out;
always_comb begin
out = a;
out[x] = b;
end
endmodule
EOF
write_verilog netlist.vOpen 7FM opened 3 hours ago
povik
commented
2 hours ago Small reproducer:
read_slang <<EOF
module top;
reg x, b;
reg [2:0] a;
reg [2:0] out;
always_comb begin
out = a;
out[x] = b;
end
endmodule
EOF
write_verilog netlist.vJust to make clear it is a write_verilog bug, there's this part in its documentation:
-noexpr
without this option all internal cells are converted to Verilog
expressions.
Version
0.46
On which OS did this happen?
Linux
Reproduction Steps
Read in CVA6 via the yosys-slang plugin and try to write it out again into a single verilog file... Not so easy to reproduce, I guess.
Expected Behavior
write_verilogshould output code without internal cells.Actual Behavior
The exported verilog code still contains
bwmuxcells. I have to manually runbwmuxmapbeforewrite_verilogto remove all internal cells.