Closed edcote closed 6 years ago
Follow up: Is there a reason why the parser craps out or this has not been implemented.
I suspect the solution is in verilog_parser.y. Never used yacc before but skipping should be trivial. Will spend a few minutes on this and report back.
BNF -->
specify_block ::= (From A.7.1)
specify { specify_item } endspecify
specify_item ::=
specparam_declaration
| pulsestyle_declaration
| showcancelled_declaration
| path_declaration
| system_timing_check
Example -->
specify
specparam tRise_clk_q = 150, tFall_clk_q = 200;
specparam tRise_control = 40, tFall_control = 50;
endspecify
Well, I have a workaround. Treat specify and endspecify as a comment.
But I am not recommending for release.
In file verilog_lexer.l
:
"specify" {
register int c;
for (;;) {
while ((c = yyinput()) != 'e' && c != EOF);
if (c == 'e') {
if ((c = yyinput()) == 'n')
if ((c = yyinput()) == 'd')
if ((c = yyinput()) == 'm')
if ((c = yyinput()) == 'o')
if ((c = yyinput()) == 'd')
if ((c = yyinput()) == 'u')
if ((c = yyinput()) == 'l')
if ((c = yyinput()) == 'e')
return TOK_SPECIFY;
}
if (c == EOF)
frontend_verilog_yyerror("endspecify keyword not found");
}
}
In verilog_parser.y
:
module_body_stmt:
[..] | specify_decl;
specify_decl:
TOK_SPECIFY
TBD if you want to close this.
@edcote , please take a look at #510 . I've added support for parsing and ignoring a subset of the specify/specparam syntax, and can extend it as needed. (I wanted something out fast first)
I've now merged the PR from @udif.
I can't possibly be the first person who hit this?
I don't care about timing info. Is there a switch that will force the parser to skip this section?