Closed rafaeltp closed 5 years ago
The error happens because the stack of the verilog parser is exhausted.
The default depth is 10000.
Your specific example can be fixed by making the following change in the source code, which increases the stack from 10000 to 15000:
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 16cac14..d3c59d0 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -39,6 +39,8 @@
#include "frontends/verilog/verilog_frontend.h"
#include "kernel/log.h"
+#define YYMAXDEPTH 15000
+
USING_YOSYS_NAMESPACE
But ultimately, if your tool concatenates 8000 signals into one vector, it might as well concatenate 80000 on a larger design, and you'll be back to square one.
No longer seeing the error on latest master, suspect this has been fixed by #1017.
Steps to reproduce the issue
I am running read_verilog on a netlist file (automatically generated by a commercial tool). A minimalist code to reproduce is:
(Note: I know the sample doesn't make sense as a verilog module, it was extracted from a much larger file)
Expected behavior
I just expect to be able to parse the line :-)
Actual behavior
I am getting the following error message: